DS08MB200 Datasheet, PDF (2/8 Pages) National Semiconductor (TI) – Dual 800 Mbps 1:2/2:1 LVDS Mux/Buffer

Pin Descriptions
Pin
Name
LLP Pin
I/O, Type
Number
Description
SWITCH SIDE DIFFERENTIAL INPUTS
SIA_0+
30
I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
SIA_0−
29
CML, or LVPECL compatible.
SIA_1+
19
I, LVDS Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
SIA_1−
20
CML, or LVPECL compatible.
SIB_0+
28
I, LVDS Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
SIB_0−
27
CML, or LVPECL compatible.
SIB_1+
21
I, LVDS Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
SIB_1−
22
CML, or LVPECL compatible.
LINE SIDE DIFFERENTIAL INPUTS
LI_0+
40
I, LVDS Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LI_0−
39
LVPECL compatible.
LI_1+
9
I, LVDS Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LI_1−
10
LVPECL compatible.
SWITCH SIDE DIFFERENTIAL OUTPUTS
SOA_0+
34
O, LVDS Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
SOA_0−
33
(Notes 1, 3).
SOA_1+
15
O, LVDS Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
SOA_1−
16
(Notes 1, 3).
SOB_0+
32
O, LVDS Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
SOB_0−
31
(Notes 1, 3).
SOB_1+
17
O, LVDS Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
SOB_1−
18
(Notes 1, 3).
LINE SIDE DIFFERENTIAL OUTPUTS
LO_0+
42
O, LVDS Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes
LO_0−
41
1, 3).
LO_1+
7
O, LVDS Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes
LO_1−
8
1, 3).
DIGITAL CONTROL INTERFACE
MUX_S0
38
I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed
MUX_S1
11
through to the Line-side.
ENA_0
36
I, LVTTL Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side
ENA_1
13
and B-side has a separate enable pin.
ENB_0
35
ENB_1
14
ENL_0
45
I, LVTTL Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a
ENL_1
4
separate enable pin.
POWER
V_DD
6, 12, 37, I, Power V_DD = 3.3V ±0.3V.
43, 48
GND
2, 3, 46, I, Power Ground reference for LVDS and CMOS circuitry.
47 (Note
For the LLP package, the DAP is used as the primary GND connection to the device. The
2)
DAP is the exposed metal contact at the bottom of the LLP-48 package. It should be
connected to the ground plane with at least 4 vias for optimal AC and thermal performance.
N/C
1, 5, 23,
No Connect
24, 25,
26, 44
Note 1: For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet.
Note 2: Note that the DAP on the backside of the LLP package is the primary GND connection for the device when using the LLP package.
Note 3: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS08MB200 device have been optimized for
point-to-point backplane and cable applications.
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