74F525 Datasheet, PDF (5/10 Pages) National Semiconductor (TI) – Programmable Counter

Timing Diagrams (Continued)
FIGURE 4 MODE 6
M_n e 110
jWith XTR HIGH the rising edge of CP loads data from the latches to the counter
TL F 9547 – 8
kWith XTR LOW the rising edge of CP begins the count and Q goes HIGH
lWhen the count reaches zero Q goes LOW and Q 2 toggles state Bringing XTR HIGH before count reaches zero will reload the counter but not affect Q
Notes
Loading Ne0 halts counter loading Ne1 will result in undefined operation
Pulse width e (2 CP) (Nb1)
FIGURE 5 MODE 7
M_n e 111
jWith XTR HIGH the rising edge of CP loads data from the latches to the counter
kOn the falling edge of XTR the rising edge of CP begins count-down
lWhen count reaches zero Q goes HIGH for one period of CP and Q 2 toggles on the Q rising edge
mOn the rising edge of CP on which Q goes LOW the counters are reloaded
nCount-down begins again
TL F 9547 – 9
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