74F525 Datasheet, PDF (2/10 Pages) National Semiconductor (TI) – Programmable Counter

Logic Symbol
Unit Loading Fan Out
Pin Names
Description
Q
Q2
M₀ – M₂
MR
CP
D₀ – D₁₅
WE
XTR
XTAL
Ouput (Primarily indicates when
the counter has reached zero)
Output (Divides Q by 2)
Status Inputs
Master Reset
Clock Pulse
Data Inputs
Write Enable Input
External Trigger Input
Crystal Output
UL
HIGH LOW
50 33 3
74F
Input I_IH I_IL
Output I_OH I_OL
b1 mA 20 mA
50 33 3
10 10
10 10
10 20
10 10
10 10
10 20
10 10
b1 mA 20 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
TL F 9547 – 1
Functional Description
The multi-function aspect of the device consists of eight
different modes of operation An explanation of the opera-
tion of the device in each of the modes follows However
there is one operation that is independent of the selected
mode the loading of data Data is latched into a set of data
latches when WE is brought from a LOW to a HIGH state
The latches are transparent when WE is held LOW
Operation Notes
1 Device should be reset before operation
2 The XTR input acts as a select line for the clock
3 With XTR low the clock goes into the counter
4 With XTR high the clock loads the counter
5 In mode 4 and 5 during counting the counter cannot be
reloaded XTR high freezes the count
6 Mode 7 is the only auto-reload mode all other modes
require and XTR pulse to begin
7 Loading 0 into the latches idles the device
MODE 0 Interval Timer with Level Output
While XTR is HIGH the data in the data latches is loaded
into the counter upon the next positive edge of CP The
negative edge of XTR enables the count-down to begin with
the next positive edge of CP When the count reaches zero
Q normally LOW is brought HIGH and Q 2 toggles state
Taking XTR HIGH at any time enables the data in the data
latches to be loaded into the counter on the rising edge of
CP and clears Q See Figure 1
MODE 1 Interval Timer with Inverted Level Output
The operation is exactly the same as in Mode 0 except that
Q is normally HIGH and goes LOW when the count reaches
zero Q 2 toggles on the negative-edge of Q See Figure 1
MODE 2 Interval Timer with Pulse Output
While XTR is HIGH the data in the data latches is loaded
into the counter upon the next positive edge of CP The
negative edge of XTR enables the count-down to begin with
the next positive edge of CP When the count reaches zero
Q normally LOW is brought HIGH for a single period of CP
Q 2 toggles state on the positive edge of Q Taking XTR
HIGH at any time causes the data in the data latches to be
loaded into the counter on the rising edge of CP and clears
Q See Figure 2
MODE 3 Interval Timer with Inverted Pulse Output
The operation is exactly the same as in Mode 2 except that
Q is normally HIGH and goes LOW for a single period of CP
Q 2 toggles on the negative edge of Q See Figure 2
2