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COP884BC Datasheet, PDF (41/57 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 2k Memory, Comparators, and CAN Interface | |||
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Interrupts (Continued)
Arbitration
Ranking
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note 18: y is VIS page, y â 0
TABLE 9. Interrupt Vector Table
Source
Software Trap
Reserved
CAN Receive
CAN Error
(transmit/receive)
CAN Transmit
Pin G0 Edge
IDLE Timer Underflow
Timer T1A/Underflow
Timer T1B
MlCROWIRE/PLUS
PWM timer
Reserved
Reserved
Reserved
Port L/Wake Up
Default VIS Interrupt
Vector Address
Hi-Low Byte
0yFEâ0yFF
0yFCâ0yFD
0yFAâ0yFB
0yF8â0yF9
0yF6â0yF7
0yF4â0yF5
0yF2â0yF3
0yF0â0yF1
0yEEâ0yEF
0yECâ0yED
0YEAâ0yEB
0yE8â0yE9
0yE6â0yE7
0yE4â0yE5
0yE2â0yE3
0yE0â0yE1
If, by accident, a VIS gets executed and no interrupt is ac-
tive, then the PC (Program Counter) will branch to a vector
located at 0yE0-0yE1.
VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active inter-
rupt is software trap, than E0 is generated. This number re-
places the lower byte of the PC. The upper byte of the PC re-
mains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration rank-
ing. This vector is read from program memory and placed
into the PC which is now pointed to the 1st instruction of the
service routine of the active interrupt with the highest arbitra-
tion ranking.
Figure 36 illustrates the different steps performed by the VIS
instruction. Figure 37 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
41
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