PC87383 Datasheet, PDF (4/77 Pages) National Semiconductor (TI) – Legacy-Reduced SuperI/O with Fast Infrared Port, Serial Port, Parallel Port and GPIOs for Portable Applications

Table of Contents
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM ........................................................................................................... 8
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY ...................................................................... 9
1.3 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 10
1.3.1 LPC Bus Interface ....................................................................................................... 10
1.3.2 Clocks .......................................................................................................................... 10
1.3.3 Parallel Port .............................................................................................................. 10
1.3.4 Infrared (IR) ................................................................................................................ 11
1.3.5 Serial Port (SP1) .......................................................................................................... 11
1.3.6 General-Purpose Input/Output (GPIO) Ports ............................................................... 12
1.3.7 Power and Ground ..................................................................................................... 12
1.3.8 Strap Configuration ...................................................................................................... 13
1.3.9 Test and Miscellaneous ............................................................................................... 13
1.4 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 14
2.0 Power, Reset and Clocks
2.1 POWER ..................................................................................................................................... 15
2.1.1 Power Planes .............................................................................................................. 15
2.1.2 Power States ............................................................................................................... 15
2.1.3 Power Connection and Layout Guidelines .................................................................. 15
2.2 RESET SOURCES AND TYPES ............................................................................................... 16
2.2.1 VDD Power-Up Reset .................................................................................................. 16
2.2.2 Hardware Reset ........................................................................................................... 16
2.3 CLOCK DOMAINS ..................................................................................................................... 16
2.3.1 LPC Domain ................................................................................................................ 16
2.3.2 48 MHz Domain ........................................................................................................... 16
2.3.3 Chip Power-Up ............................................................................................................ 17
2.3.4 Specifications .............................................................................................................. 17
2.4 TESTABILITY SUPPORT .......................................................................................................... 17
2.4.1 ICT ............................................................................................................................... 17
2.4.2 XOR Tree Testing ........................................................................................................ 17
2.4.3 Test Mode Entry Sequence ......................................................................................... 18
3.0 Device Architecture and Configuration
3.1 OVERVIEW ............................................................................................................................... 19
3.2 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 19
3.2.1 The Index-Data Register Pair ...................................................................................... 19
3.2.2 Banked Logical Device Registers Structure ................................................................ 20
3.2.3 Standard Configuration Register Definitions ............................................................... 21
3.2.4 Standard Configuration Registers ............................................................................... 23
3.2.5 Default Configuration Setup ........................................................................................ 24
3.3 MODULE CONTROL ................................................................................................................. 25
3.3.1 Module Enable/Disable ................................................................................................ 25
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Revision 1.1