PC87334VLJ Datasheet, PDF (4/102 Pages) National Semiconductor (TI) – SuperI/O 3.3V/5V Floppy Disk Controller, Dual UARTs, Infrared, IEEE1284 Parallel Port, and IDE Interface

Table of Contents (Continued)
6 0 SERIAL PORTS
6 1 Serial Port Registers
6 2 Line Control Register (LCR)
6 3 Programmable Baud Rate Generator
6 4 Line Status Register (LSR)
6 5 FIFO Control Register
6 6 Interrupt Identification Register (IIR)
6 7 Interrupt Enable Register (IER)
6 8 MODEM Control Register (MCR)
6 9 MODEM Status Register (MSR)
6 10 Scratchpad Register (SCR)
7 0 PARALLEL PORT
7 1 Introduction
7 2 Data Register (DTR)
7 3 Status Register (STR)
7 4 Control Register (CTR)
7 5 Enhanced Parallel Port Operation
7 6 Extended Capabilities Parallel Port (ECP)
7 6 1 Introduction
7 6 2 Software Operation
7 7 Register Definitions
7 8 Software Controlled Data Transfer (Modes 000 and
001)
7 9 Automatic Data Transfer (Modes 010 and 011)
7 9 1 Forward Direction (Bit 5 of DCRe0)
7 9 2 ECP (Forward) Write Cycle
7 9 3 Backward Direction (bit 5 of DCR is 1)
7 9 4 ECP (Backward) Read Cycle
7 10 FIFO Test Access (Mode 110)
7 11 Configuration Registers Access (Mode 111)
7 12 Interrupt Generation
8 0 INTEGRATED DEVICE ELECTRONICS
INTERFACE (IDE)
8 1 Introduction
8 2 IDE Signals
9 0 SERIAL INFRARED INTERFACE (SIR)
10 0 ELECTRICAL CHARACTERISTICS
10 1 DC Electrical Characteristics
10 2 DC Electrical Characteristics
10 3 AC Electrical Characteristics
10 3 1 AC Test Conditions
10 3 2 Clock Timing
10 3 3 Microprocessor Interface Timing
10 3 4 Baud Out Timing
10 3 5 Transmitter Timing
10 3 6 Receiver Timing
10 3 7 MODEM Control Timing
10 3 8 DMA Timing
10 3 9 Reset Timing
10 3 10 Write Data Timing
10 3 11 Drive Control Timing
10 3 12 Read Data Timing
10 3 13 IDE Timing
10 3 14 Parallel Port Timing
10 3 15 Enhanced Parallel Port Timing
10 3 16 Extended Capabilities Port Timing
10 3 17 3F3 Read Timing
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