PC87334VLJ Datasheet, PDF (32/102 Pages) National Semiconductor (TI) – SuperI/O 3.3V/5V Floppy Disk Controller, Dual UARTs, Infrared, IEEE1284 Parallel Port, and IDE Interface

3 0 FDC Register Description (Continued)
D4 5
D3 2
Drive ID0 1 (For Enhanced mode)
Bits 4 and 5 are read only bits which hold the val-
ues of pins DRID0 1
Bits 3 and 2 are read write bits that control logical
drive exchange
When working in four drive encoded mode (bit 4 of
FER is 1) the logical drive exchange is not per-
formed
00 No logical drive exchange
01 Logical drive exchange between drives 0 and 1
as selected by bit 4 of FCR
10 Logical drive exchange between drives 0 and 2
This bit allows software to exchange the physi-
cal floppy disk control signals assigned to drive
0 and 2 Under these conditions the DR0
DR23 and MTR0 pin functions are as follows
DR2 internal signal to DR0 pin
MTR2 internal signal to MTR0 pin
DR0 internal signal to DR23 pin
Note Drive 3 is not exchanged at the same time as Drive 2
11 Reserved Unpredictable results when 11 is
configured
D1 0
Tape Select 1 0 These bits assign a logical drive
number to a tape drive Drive 0 is not available as a
tape drive and is reserved as the floppy disk boot
drive See Table 3-4 for the tape drive assignment
values
TABLE 3-4 Media ID Bit Functions
Bit 7
Bit 6
Bit 5
Media Type
X
X
1
Invalid Data
0
0
0
5 25
0
1
0
2 88M
1
0
0
1 44M
1
1
0
720k
TABLE 3-5 Tape Drive Assignment Values
TAPESEL1
0
0
1
1
TAPESEL0
0
1
0
1
Drive
Selected
None
1
2
3
Mode
Compatible AT TDR
Automatic Media Sense
Enhanced
FCR
Bit 0
1
0
0
or
1
ASC
Bit 2
0
0
1
TABLE 3-3 TDR Operation Modes
TDR
D7 D6
D5
D4
Bit
DESC X
X
X
X
RESET
COND ^{N A N A N A}
NA
DESC ED HD ^VALID
X
DATA
RESET _{N A N A N A}
NA
COND
DESC ED HD DRID1 DRID0
RESET
NA NA NA
NA
COND
D3
X
NA
X
NA
SWP1
0
D2
X
NA
X
NA
SWP0
0
D1
TAPE
SEL 1
0
TAPE
SEL 1
0
TAPE
SEL 1
0
D0
TAPE
SEL 0
0
TAPE
SEL 0
0
TAPE
SEL 0
0
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