PC87334VLJ Datasheet, PDF (10/102 Pages) National Semiconductor (TI) – SuperI/O 3.3V/5V Floppy Disk Controller, Dual UARTs, Infrared, IEEE1284 Parallel Port, and IDE Interface

1 0 Pin Description (Continued)
TABLE 1-1 Pin Descriptions (Alphabetical)
Symbol
PQFP TQFP
IO
Pin
Pin
Function
3F3RD
56
54
O 3F3 Read This pin is used to implement the 3F3 Tape Drive Register (TDR) externally
3F3RD is active when read PIO from 3F3 hex address is active (A10 is not decoded) and
AEN e 0 This pin is configured when bit 1 of Function Control Register (FCR) is 1 (This
pin is shared with the IDEHI IRTX and DRID1 signals )
ADRATE0 1 98 48 96 46 O Additional Data Rate 0 1 These outputs are similar to DRATE0 1 They are provided in
addition to DRATE0 1 They reflect the currently selected FDC data rate (bits 0 and 1 in
the Configuration Control Register (CCR) or the Data Rate Select Register (DSR)
whichever was written to last) ADRATE0 is configured when bit 0 of ASC is 1 ADRATE1
is configured when bit 4 of the Advanced SIO Configuration Register (ASC) is 1 (These
pins are shared with the IRQ5 and DENSEL signals )
A10 – A0
21 – 31 19– 29 I Address These microprocessor address lines determine which internal register is
accessed A0–A10 are don’t cares during a DMA transfer
ACK
85
83
I Acknowledge This input is pulsed low by a connected printer to indicate that it has
received data from the parallel port This pin has a nominal 25 kX pull-up resistor attached
to it (This pin is shared with DR1 See Table 7-5 for further information )
AFD
78
76 I O Automatic Feed XT When this signal is low the connected printer should automatically
line feed after each line is printed This pin is in a TRI-STATE condition 10 ns after a 0 is
loaded into the corresponding Control Register bit The system should pull this pin high
using a 4 7 kX resistor (See DSTRB and Table 7-5 for further information )
AEN
20
18
I Address Enable This input disables function selection via A10 – A0 when it is high
Access during DMA transfer is NOT affected by this pin
ASTRB
81
79
O Address Strobe This signal is used in EPP mode as an address strobe It is active low
(See SLIN and Table 7-5 for further information )
BADDR0 1
BOUT1 2
55 58 53 56
73 65 71 63
I Base Address These bits determine one of four base addresses from which the Index
and Data Registers are offset (See Table 2-2) An internal pull-down resistor of 30 kX is
present on this pin Use a 10 kX resistor to pull this pin to V_CC
O BAUD Output This multi-function pin provides the associated serial channel Baud Rate
generator output signal when test mode is selected in the Power and Test Configuration
Register and the DLAB bit (LCR7) is set After Master Reset this pin provides the SOUT
function (See SOUT and CFG0 – 4 for further information )
BUSY
84
82
I Busy This pin is set high by the printer when it cannot accept another character It has a
nominal 25 kX pull-down resistor attached to it (See WAIT and Table 7-5 for further
information )
CFG0 – 4
65 66 63 64 I Configuration on Power-up These CMOS inputs select 1 of 32 default configurations in
71 73 69 71
which the PC87334VLJ PC87334VJG powers-up (See Table 2-1) An internal pull-down
74
72
resistor of 30 kX is present on each pin Use a 10 kX resistor to pull these pins to V_CC
CLK48
57
55
I Clock 48 This pin is the CLK48 reset strap option During reset the value of this pin is
latched into bit 0 of TUP (CLK48 bit) A 30 kX internal pull-down resistor is present on this
pin Use a 10 kX resistor to pull it high during reset
CTS1 2
72 64 70 62 I Clear to Send When low this indicates that the MODEM or data set is ready to exchange
data The CTS signal is a MODEM status input whose condition the CPU can test by
reading bit 4 (CTS) of the MODEM Status Register (MSR) for the appropriate serial
channel Bit 4 is the complement of the CTS signal Bit 0 (DCTS) of the MSR indicates
whether the CTS input has changed state since the previous reading of the MSR CTS has
no effect on the transmitter
Note Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled
D7 – D0
10 – 17 8– 15 I O Data Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB
These signals all have 24 mA (sink) buffered outputs
10