DS92LV18 Datasheet, PDF (4/20 Pages) National Semiconductor (TI) – 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

Serializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
DO ± HIGH to
t_HZD
TRI-STATE Delay
2.3
DO ± LOW to
t_LZD
TRI-STATE Delay
Figure 7 (Note 4)
1.9
t_ZHD
DO ± TRI-STATE to
HIGH Delay
R_L = 100Ω,
C_L=10pF to GND
1.0
DO ± TRI-STATE to
t_ZLD
LOW Delay
1.0
t_SPW
t_PLD
t_SD
t_RJIT
SYNC Pulse Width
Serializer PLL Lock Time
Serializer Delay
Random Jitter
Figure 9,
R_L = 100Ω
Figure 8,
R_L = 100Ω
Figure 10 , R_L = 100Ω
Room Temp., 3.3V,
66 MHz
5*t_TCP
510*t_TCP
t_TCP + 1.0
t_TCP + 2.0
4.5
t_DJIT
Deterministic Jitter
Figure 16, (Note 8)
15 MHz
66 MHz
-430
-40
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_RFCP
t_RFDC
t_RFCP /
t_TCP
t_RFTT
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to
TCLK
REFCLK Transition Time
15.2
T
40
50
0.95
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
t_RCP
Receiver out Clock
Period
t_RCP = t_TCP
RCLK
15.2
t_RDC
t_CLH
t_CHL
t_ROS
t_ROH
RCLK Duty Cycle
CMOS/TTL
Low-to-High
Transition Time
CMOS/TTL
High-to-Low
Transition Time
ROUT (0-9) Setup
Data to RCLK
ROUT (0-9) Hold
Data to RCLK
RCLK
45
CL = 15 pF
Figure 4
Figure 12
ROUT(0-17),
LOCK,
RCLK
0.35*t_RCP
−0.35*t_RCP
50
2.2
2.2
0.5*t_RCP
−0.5*t_RCP
Max
10
10
10
10
6*t_TCP
1024*t_TCP
t_TCP + 4.0
190
70
Max
66.7
60
1.05
6
Max
66.7
55
4
4
Units
ns
ns
ns
ns
ns
ns
ns
ps
(RMS)
ps
ps
Units
ns
%
ns
Units
ns
%
ns
ns
ns
ns
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