DS92LV18 Datasheet, PDF (1/20 Pages) National Semiconductor (TI) – 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

October 2003
DS92LV18
18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz
General Description
The DS92LV18 Serializer/Deserializer (SERDES) pair trans-
parently translates a 18–bit parallel bus into a BLVDS serial
stream with embedded clock information. This single serial
stream simplifies transferring a 18-bit, or less, bus over PCB
traces and cables by eliminating the skew problems between
parallel data and clock paths. It saves system cost by nar-
rowing data paths that in turn reduce PCB layers, cable
width, and connector size and pins.
This SERDES pair includes built-in system and device test
capability. The line loopback feature enables the user to
check the integrity of the serial data transmission paths of
the transmitter and receiver while deserializing the serial
data to parallel data at the receiver outputs. The local loop-
back feature enables the user to check the integrity of the
transceiver from the local parallel-bus side.
The DS92LV18 incorporates modified BLVDS signaling on
the high-speed I/O. BLVDS provides a low power and low
noise environment for reliably transferring data over a serial
transmission path. The equal and opposite currents through
the differential data path control EMI by coupling the result-
ing fringing fields together.
Features
n 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376
Gbps full duplex throughput)
n Independent transmitter and receiver operation with
separate clock, enable, and power down pins
n Hot plug protection (power up high impedance) and
synchronization (receiver locks to random data)
n Wide ±5% reference clock frequency tolerance for easy
system design using locally-generated clocks
n Line and local loopback modes
n Robust BLVDS serial transmission across backplanes
and cables for low EMI
n No external coding required
n Internal PLL, no external PLL components required
n Single +3.3V power supply
n Low power: 90mA (typ) transmitter, 100mA (typ) at 66
MHz with PRBS-15 pattern
n ±100 mV receiver input threshold
n Loss of lock detection and reporting pin
n Industrial −40 to +85˚C temperature range
n >2.0kV HBM ESD
n Compact, standard 80-pin PQFP package
Block Diagram
DS92LV18
© 2003 National Semiconductor Corporation DS200312
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