DS92LV18 Datasheet, PDF (14/20 Pages) National Semiconductor (TI) – 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

Resynchronization (Continued)
The user can choose to resynchronize to the random data
stream or to force fast synchronization by pulsing the Seri-
alizer’s SYNC pin. Lock times depend on serial data stream
characteristics. The primary constraint on the "random" lock
time is the initial phase relation between the incoming data
and the REFCLK when the Deserializer powers up. An ad-
vantage of using the SYNC pattern to force synchronization
is the ability for the user to predict the delay before the PLL
regains lock. This scheme is left up to the user discretion.
One recommendation is to provide a feedback loop using the
LOCK pin itself to control the sync request of the Serializer,
which is the SYNC pin.
If a specific pattern is repetitive, the Deserializer’s PLL will
not lock in order to prevent the Deserializer from locking to
the data pattern rather than the clock. We refer to such
pattern as a repetitive multi-transition, RMT. This occurs
when more than one Low-High transition takes places in a
clock cycle over multiple cycles. This occurs when any bit,
except DIN 17, is held at a low state and the adjacent bit is
held high, creating a 0-1 transition. The internal circuitry
accomplishes this by detecting more than one potential po-
sition for clocking bits. Upon detection, the circuitry will pre-
vent the LOCK output from becoming active until the RMT
pattern changes. Once the RMT pattern changes and the
internal circuitry recognizes the clock bits in the serial data
stream, the PLL of the Deserializer will lock, which will drive
the LOCK output to low and the output data ROUTn will
become valid.
Powerdown
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer will occupy while waiting for ini-
tialization. You can also use TPWDN and RPWDN to reduce
power when there are no pending data transfers. The Dese-
rializer enters powerdown mode when RPWDN is driven low.
In powerdown mode, the PLL stops and the outputs enter
TRI-STATE, which reduces supply current to the µA range.
To bring the Deserializer block out of the Powerdown state,
the system drives RPWDN high. When the Deserializer exits
Powerdown, it automatically enters the Initialization state.
The system must then allow time for Initialization before data
transfer can begin.
The TPWDN pin driven low forces the Serializer block into
low power consumption, where the supply current is in the
µA range. The Serializer PLL stops and the output goes into
a TRI-STATE condition.
To bring the Serializer block out of the powerdown state, the
system drives TPWDN high. When the Serializer exits Pow-
erdown, its PLL must lock to TCLK before it is ready for the
Initialization state. The system must then allow time for
Initialization before data transfer can begin.
TRI-STATE
When the system drives the REN pin low, the Deserializer’s
outputs enter TRI-STATE. This will TRI-STATE the receiver
output pins (ROUT[0:17]) and RCLK. When the system
drives REN high, the Deserializer will return to the previous
state as long as all other control pins remain static (RP-
WDN).
When the system drives the DEN pin low, the Serializer’s
LVDS outputs enter TRI-STATE. When the system drives the
DEN signal high, the Serializer output will return to the
previous state as long as all other control and data input pins
remain in the same condition before DEN was driven low.
Loopback Test Operation
The DS92LV18 includes two Loopback modes for testing the
device functionality and the transmission line continuity. As-
serting the Line Loopback control signal connects the serial
data input (RIN±) to the serial data output (DO±) and to the
parallel data output (ROUT[0:17]). The serial data goes
through deserializer and serializer blocks.
Asserting the Local Loopback control signal connects the
parallel data input (DIN[0:17]) back to the parallel data out-
put (ROUT[0:17]). The connection route includes all the
functional blocks of the SER/DES Pair. The serial data out-
put (DO±) is automatically disabled during the Local Loop-
back operating mode.
Please note that when switching between normal, line, or
loopback modes, the deserializer will need to relock. In order
for the serializer and deserializer to resync, the TCLK and
REFCLK frequencies must be within ±5% of each other.
Application Information
USING THE DS92LV18
The DS92LV18 combines a Serializer and Deserializer onto
a single chip that sends 18 bits of parallel TTL data over a
serial Bus LVDS link up to 1.32 Gbps. Serialization of the
input data is accomplished using an on-board PLL at the
Serializer which embeds two clock bits with the data. The
Deserializer uses a separate reference clock (REFCLK) and
an on-board PLL to extract the clock information from the
incoming data stream and deserialize the data. The Deseri-
alizer monitors the incoming clock information to determine
lock status and will indicate loss of lock by asserting the
LOCK output high.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the LVDS outputs minimize the
slope of the speed vs. I_CC curve of CMOS designs.
POWERING UP THE DESERIALIZER
The REFCLK input can be running before the Deserializer is
powered up and it must be running in order for the Deseri-
alizer to lock to incoming data. The Deserializer outputs will
remain in TRI-STATE until the Deserializer detects data
transmission at its inputs and locks to the incoming serial
data stream.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, V_CC noise (noise bandwidth and
out-of-band noise)
Media: ISI, V_CM noise
Deserializer: V_CC noise
For a graphical representation of noise margin, please see
Figure 17.
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