DS90UR124_08 Datasheet, PDF (4/30 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
(Figure 5)
(Note 8), (Figure 4)
(Note 9)
23.25
0.3T
0.3T
T
0.5T
0.5T
2.5
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_LLHT
t_LHLT
t_DIS
t_DIH
t_HZD
t_LZD
t_ZHD
t_ZLD
t_PLD
t_SD
LVDS Low-to-High Transition Time R_L = 100Ω, VODSEL = L,
245
LVDS High-to-Low Transition Time C_L = 10 pF to GND, (Figure 3)
264
D_IN (0:23) Setup to TCLK
D_IN (0:23) Hold from TCLK
R_L = 100Ω, C_L = 10 pF to GND,
4
(Note 8), (Figure 5)
4
D_OUT ± HIGH to TRI-STATE Delay R_L = 100Ω,
10
D_OUT ± LOW to TRI-STATE Delay C_L = 10 pF to GND,
10
D_OUT ± TRI-STATE to HIGH Delay ^{(Note 5), (Figure 6)}
75
D_OUT ± TRI-STATE to LOW Delay
75
Serializer PLL Lock Time
R_L = 100Ω
Serializer Delay
R_L = 100Ω, PRE = OFF,
RAOFF = L, TRFB = H,
3.5T+2
(Figure 8)
R_L = 100Ω, PRE = OFF,
RAOFF = L, TRFB = L,
(Figure 8)
3.5T+2
TxOUT_E_O TxOUT_Eye_Opening.
5 MHz–43 MHz,
TxOUT_E_O centered on (tBIT/)2 R_L = 100Ω, C_L = 10 pF to GND,
0.76
0.84
RANDOM pattern
(Notes 9, 10, 13), (Figure 9)
Max
200
0.7T
0.7T
±100
Units
ns
ns
ns
ns
ps
Max
Units
550
ps
550
ps
ns
ns
15
ns
15
ns
150
ns
150
ns
10
ms
3.5T+10 ns
3.5T+10 ns
UI
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
t_RCP
Receiver out Clock Period
t_RCP = t_TCP,
PTOSEL = H
RCLK
(Figure 15)
23.25
t_RDC
RCLK Duty Cycle
PTOSEL = H,
45
SLEW = L
t_CLH
LVCMOS Low-to-High
C_L = 4 pF
R_OUT [0:23],
Transition Time
(lumped load), RCLK, LOCK
t_CHL
LVCMOS High-to-Low
SLEW = H
Transition Time
(Note 8)
t_CLH
LVCMOS Low-to-High
C_L = 4 pF
R_OUT [0:23],
Transition Time
(lumped load), RCLK, LOCK
t_CHL
LVCMOS High-to-Low
SLEW = L
Transition Time
(Note 8)
t_ROS
R_OUT (0:7) Setup Data to
PTOSEL = L,
R_OUT[0:7]
(0.35)*
RCLK (Group 1)
SLEW = H,
t_RCP
t_ROH
R_OUT (0:7) Hold Data to RCLK ^{(Figure 16)}
(0.35)*
(Group 1)
t_RCP
Typ
T
50
1.5
1.5
2.0
2.0
(0.5*t_RCP)–3 UI
(0.5*t_RCP)–3 UI
Max Units
200
ns
55
%
2.5
ns
2.5
ns
3.5
ns
3.5
ns
ns
ns
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