DS90UR124_08 Datasheet, PDF (15/30 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS90UR124 Deserializer Pin Descriptions
Pin # Pin Name I/O/PWR
Description
LVCMOS PARALLEL INTERFACE PINS
35-38, R_OUT[7:0]
41-44
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1
19-22, R_OUT[15:8]
27-30
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2
7-10, R_OUT[23:16] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3
13-16
24 RCLK
LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
55 RRFB
60 REN
LVCMOS_I
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; R_OUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; R_OUT LVCMOS Outputs strobed on the Falling Clock Edge.
Receiver Data Enable
REN = H; R_OUT[23-0] and RCLK are Enabled (ON).
REN = L; R_OUT[23-0] and RCLK are Disabled (OFF), Receiver R_OUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
48 RPWDNB LVCMOS_I Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), R_OUT[23-0], RCLK, and LOCK are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
49 PTOSEL
LVCMOS_I
Progressive Turn On Operation Selection
PTO = H; R_OUT[23:0] are grouped into three groups of eight, with each group switching about
±1 UI to ±2 UI apart relative to RCLK. (Figure 15)
PTO = L; PTO Spread Mode, R_OUT[23:0] outputs are spread ±1 UI to ±2 UI and RCLK spread
±1 UI. (Figure 16)
See Applications Informations section for more details.
63 RAOFF
LVCMOS_I
Randomizer Control Input Pin
RAOFF = H, Backwards compatible mode for use with DS90C241 Serializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
See Table 2 for more details.
64 SLEW
LVCMOS_I
LVCMOS Output Slew Rate Control
SLEW = L; Low drive output at 2 mA (default)
SLEW = H; High drive output at 4 mA
23 LOCK
50 RES0
LVCMOS_O
LVCMOS_I
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, R_OUT[23-0] and RCLK are TRI-STATED
Reserved. This pin MUST be tied LOW.
1-6, RES0
NC
17, 18,
33, 34
No Connection. Pins are not physically connected to the die. Recommendation is to leave pin
open or tie it to LOW.
BIST MODE PINS
61 BISTEN
LVCMOS_I
Control Pin for BIST Mode Enable
BISTEN = L; Default at Low, Normal Mode.
BISTEN = H; BIST mode active. When BISTEN = H and DS90UR241 DIN[23:0] = Low or
Floating; device will go to BIST mode accordingly. Check PASS output pin for test status. See
Applications Informations section for more details.
62 BISTM
LVCMOS_I
BIST Mode selection. Control pin for which Deserializer is set for BIST reporting mode.
BISTM = L; Default at Low, Status of all R_OUT with respective bit error on cycle-by-cycle basis
BISTM = H; Total accumulated bit error count provided on ROUT[7:0] (binary counter up to 255)
See Applications Informations section for more details.
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