DS90UR124_08 Datasheet, PDF (16/30 Pages) National Semiconductor (TI) – 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Pin # Pin Name
I/O/PWR
45 PASS
LVCMOS_O
LVDS SERIAL INTERFACE PINS
53
R_IN+
LVDS_I
54
R_IN−
LVDS_I
POWER / GROUND PINS
51 VDD
VDD
52 VSS
GND
59 VDD
VDD
58 VSS
GND
57 VDD
VDD
56 VSS
GND
32 VDD
VDD
31 VSS
GND
46 VDD
VDD
47 VSS
GND
40 VDD
VDD
39 VSS
GND
26 VDD
VDD
25 VSS
GND
11 VDD
VDD
12 VSS
GND
Description
Pass flag output for @Speed BIST Test operation.
PASS = L; BIST failure
PASS = H; LOCK = H before BIST can be enabled, then 1x10^-9 error rate achieved across link
See Applications Informations section for more details.
Receiver LVDS True (+) Input
This input is intended to be terminated with a 100Ω load to the R_IN+ pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
Receiver LVDS Inverted (−) Input
This input is intended to be terminated with a 100Ω load to the R_IN- pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
Analog LVDS Voltage Supply, POWER
Analog LVDS GROUND
Analog Voltage Supply, PLL POWER
Analog Ground, PLL GROUND
Analog Voltage supply, PLL VCO POWER
Analog Ground, PLL VCO GROUND
Digital Voltage Supply, LOGIC POWER
Digital Ground, Logic GROUND
Digital Voltage Supply, LOGIC POWER
Digital Ground, LOGIC GROUND
Digital Voltage Supply, LVCMOS Output POWER
Digital Ground, LVCMOS Output GROUND
Digital Voltage Supply, LVCMOS Output POWER
Digital Ground, LVCMOS Output GROUND
Digital Voltage Supply, LVCMOS Output POWER
Digital Ground, LVCMOS Output GROUND
www.national.com
16