DS90CR288A Datasheet, PDF (4/20 Pages) National Semiconductor (TI) – 28-Bit Channel Link-85MHz

ؾితಛੑ ( ͖ͭͮ)
ಛهͷͳ͍ݶΓɺਪ঑ಈ࡞ిిݯѹ͓Αͼಈ࡞Թ౓ൣғʹରͯ͠ద༻ɻ
Symbol
Parameter
Conditions
ɹTRANSMITTER SUPPLY CURRENT
I_CCTW Transmitter Supply Current Worst
Case (with Loads)
R_L ʹ 100Њ,
C_L ʹ 5 pF,
Worst Case Pattern
(Figure 1ɺ2 )
f ʹ 33 MHz
f ʹ 40 MHz
f ʹ 66 MHz
f ʹ 85 MHz
I_CCTZ
Transmitter Supply Current Power
Down
PWR DWN ʹ Low
Driver Outputs in TRI-STATE
under Powerdown Mode
ɹRECEIVER SUPPLY CURRENT
I_CCRW Receiver Supply Current Worst Case
C_L ʹ 8 pF,
Worst Case Pattern
(Figure 1ɺ3)
f ʹ 33 MHz
f ʹ 40 MHz
f ʹ 66 MHz
f ʹ 85 MHz
I_CCRZ
Receiver Supply Current Power Down _{PWR DWN ʹ Low}
Receiver Outputs Stay Low during
Powerdown Mode
Min Typ Max Units
31
45
mA
32
50
mA
37
55
mA
42
60
mA
10
55
ЖA
49
70
mA
53
75
mA
81
114 mA
96
135 mA
140 400 ЖA
Note 1: ʮઈର࠷େఆ֨ʯͱ͸ɺ͜ͷൣғΛ௒͑ΔͱσόΠεͷ҆શੑ͕อূ͞Εͳ͍Ϧϛοτ஋Λ͍͍ɺ͜ΕΒͷϦϛοτ஋ͰσόΠε͕ಈ࡞͢Δ͜ͱΛҙຯ͢Δ΋
ͷͰ͸͋Γ·ͤΜɻిؾతಛੑͷදʹσόΠεͷ࣮ಈ࡞৚݅Λ͢·͍ͯ͠ࡌهɻ
Note 2:
Note 3:
୅ද஋ (Typ) ͸શͯ V_CC ʹ 3.3VɺT_A ʹʴ 25 ˆͰಘΒΕΔ࠷΋ඪ४తͳ਺஋Ͱ͢ɻ
σόΠε୺ࢠʹྲྀΕࠐΉిྲྀ͸ਖ਼ɺσόΠε୺ࢠ͔ΒྲྀΕग़Δిྲྀ͸ෛͱఆٛ͞Ε·͢ɻV_OD ͱ϶V_OD Ҏ֎ɺશͯͷిѹ஋͸άϥ΢ϯυ୺ࢠΛج४ͱ
͠·͢ɻ
Note 4: V_OS ͸Ҏલ͸ V_CMͱද͞هΕ͍ͯ·ͨ͠ɻ
τϥϯεϛολɾεΠονϯάಛੑ
ಛهͷͳ͍ݶΓɺਪ঑ಈ࡞ిిݯѹ͓Αͼಈ࡞Թ౓ൣғʹରͯ͠ద༻ɻ
Symbol
LLHT
LHLT
TCIT
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
Parameter
LVDS Low-to-High Transition Time (Figure 2)
LVDS High-to-Low Transition Time (Figure 2)
TxCLK IN Transition Time (Figure 4)
Transmitter Output Pulse Position for Bit0 (Figure 14)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 5)
TxCLK IN High Time (Figure 5)
TxCLK IN Low Time (Figure 5)
TxIN Setup to TxCLK IN (Figure 5)
TxIN Hold to TxCLK IN (Figure 5)
TxCLK IN to TxCLK OUT Delay (Figure 7)
TPLLS
TPDD
TJIT
Transmitter Phase Lock Loop Set (Figure 9)
Transmitter Powerdown Delay (Figure 12)
TxCLK IN Cycle-to-Cycle Jitter (Input clock requirement)
f ʹ 85 MHz
f ʹ 85 MHz
T_A ʹ 25 ˆ ,
V_CC ʹ 3.3V
Min
1.0
ʵ 0.20
1.48
3.16
4.84
6.52
8.20
9.88
11.76
0.35T
0.35T
2.5
0
3.8
Typ
0.75
0.75
0
1.68
3.36
5.04
6.72
8.40
10.08
T
0.5T
0.5T
Max
1.5
1.5
6.0
0.20
1.88
3.56
5.24
6.92
8.60
10.28
50
0.65T
0.65T
6.3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ms
100
ns
2
ns
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