DS90CR283 Datasheet, PDF (4/14 Pages) National Semiconductor (TI) – 28-Bit Channel Link-66 MHz

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
RECEIVER SUPPLY CURRENT
I_CCRW
Receiver Supply Current,
Worst Case
I_CCRZ
Receiver Supply Current,
Power Down
Conditions
Min
Typ
Max Units
C_L = 8 pF,
Worst Case Pattern
f = 32.5 MHz
f = 37.5 MHz
(Figures 1, 3)
f = 66 MHz
Power Down = Low
Receiver Outputs in Previous State
during Power Down Mode
64
77
mA
70
85
mA
110
140
mA
1
10
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 5.0V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V_OD and ∆V _OD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V_CC ≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Note 5: V_OS previously referred as V_CM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
Parameter
LVDS Low-to-High Transition Time (Figure 2)
LVDS High-to-Low Transition Time (Figure 2)
TxCLK IN Transition Time (Figure 4)
TxOUT Channel-to-Channel Skew (Note 6) (Figure 5)
Transmitter Output Pulse Position for Bit 0
f = 66 MHz
(Figure 16)
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 6)
TxCLK IN High Time (Figure 6)
TxCLK IN Low Time (Figure 6)
TxIN Setup to TxCLK IN (Figure 6)
TxIN Hold to TxCLK IN (Figure 6)
TxCLK IN to TxCLK OUT Delay @ 25˚C,
V_CC = 5.0V (Figure 8)
Transmitter Phase Lock Loop Set (Figure 10)
Transmitter Power Down Delay (Figure 14)
Min
−0.30
1.70
3.60
5.90
8.30
10.40
12.70
15
0.35T
0.35T
5
2.5
3.5
Note 6: This limit based on bench characterization.
Typ
0.75
0.75
0
(1/7)T_clk
(2/7)T_clk
(3/7)T_clk
(4/7)T_clk
(5/7)T_clk
(6/7)T_clk
T
0.5T
0.5T
3.5
1.5
Max
1.5
1.5
8
350
0.30
2.50
4.50
6.75
9.00
11.10
13.40
50
0.65T
0.65T
8.5
10
100
Units
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
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