DS90CR283 Datasheet, PDF (10/14 Pages) National Semiconductor (TI) – 28-Bit Channel Link-66 MHz

DS90CR283 Pin Description — Channel Link Transmitter
Pin Name I/O No.
TxIN
I 28
TxOUT+
O4
TxOUT−
O4
TxCLK IN
I
1
TxCLK OUT+ O 1
TxCLK OUT− O 1
PWR DOWN
I
1
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I
4
I
5
I
1
I
2
I
1
I
3
Description
TTL Level inputs
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The rising edge acts as data strobe
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down
Power supply pins for TTL inputs
Ground pins for TTL inputs
Power supply pin for PLL
Ground pins for PLL
Power supply pin for LVDS outputs
Ground pins for LVDS outputs
DS90CR284 Pin Description — Channel Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
I
4
I
4
O 28
I
1
I
1
O1
I
1
I
4
I
5
I
1
I
2
I
1
I
3
Description
Positive LVDS differential data inputs
Negative LVDS differential data inputs
TTL level outputs
Positive LVDS differential clock input
Negative LVDS differential clock input
TTL level clock output. The rising edge acts as data strobe
TTL level input. Assertion (low input) maintains the receiver outputs in the previous state
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply for PLL
Ground pin for PLL
Power supply pin for LVDS inputs
Ground pins for LVDS inputs
Applications Information
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For ex-
ample, for lower data rate (clock rate) and shorter cable
lengths (< 2m), the media electrical performance is less criti-
cal. For higher speed/long distance applications the media’s
performance becomes more critical. Certain cable construc-
tions provide tighter skew (matched electrical length be-
tween the conductors and pairs). Twin-coax for example, has
been demonstrated at distances as great as 5 meters and
with the maximum data transfer of 1.848 Gbit/s. Additional
applications information can be found in the following Na-
tional Interface Application Notes:
AN = ####
AN-1041
AN-1035
AN-806
Topic
Introduction to Channel Link
PCB Design Guidelines for LVDS and
Link Devices
Transmission Line Theory
AN = ####
Topic
AN-905
Transmission Line Calculations and
Differential Impedance
AN-916
Cable Information
CABLES: A cable interface between the transmitter and re-
ceiver needs to support the differential LVDS pairs. The
21-bit CHANNEL LINK chipset (DS90CR213/214) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR283/284) requires five pairs of signal wires.
The ideal cable/connector interface would have a constant
100Ω differential impedance throughout the path. It is also
recommended that cable skew remain below 350 ps (@ 66
MHz clock rate) to maintain a sufficient data sampling win-
dow at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some
of the more commonly used cable types for point-to-point ap-
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