CD4042BM Datasheet, PDF (4/6 Pages) National Semiconductor (TI) – Quad Clocked D Latch

AC Electrical Characteristics
T_A e 25 C C_L e 50 pF R_L e 200k Input t_r e t_f e 20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL t_PLH
Propagation Delay Time Data In to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
175
350
ns
75
150
ns
60
120
ns
t_PHL t_PLH
Propagation Delay Time Data In to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
150
300
ns
75
150
ns
50
100
ns
t_PHL t_PLH
Propagation Delay Time Clock to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
250
500
ns
100
200
ns
80
160
ns
t_PHL t_PLH
Propagation Delay Time Clock to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
250
500
ns
115
230
ns
90
180
ns
t_H
Minimum Hold Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
60
120
ns
30
60
ns
25
50
ns
t_SU
Minimum Setup Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
0
50
ns
0
30
ns
0
25
ns
t_W
Minimum Clock Pulse Width
V_DD e 5V
V_DD e 10V
V_DD e 15V
100
200
ns
50
100
ns
30
60
ns
t_THL t_TLH
Transition Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
125
250
ns
60
125
ns
50
100
ns
C_IN
Input Capacitance
Any Input
50
75
pF
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the
devices should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual
device operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 Being a latch the CD4042BM CD4042BC is not clock rise and fall time sensitive
Note 4 I_OH and I_OL are tested one output at a time
4