CD4042BM Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Quad Clocked D Latch

DC Electrical Characteristics CD4042BC (Note 2)
Symbol
Parameter
Conditions
b40 C
a25 C
a85 C
Units
Min Max Min Typ Max Min Max
I_DD
Quiescent Device Current V_DD e 5V
V_DD e 10V
V_DD e 15V
4
0 02 4
30 mA
8
0 02 8
60 mA
16
0 02 16
120 mA
V_OL
l l ^{Low Level Output Voltage I}O ^{k 1 mA V}IH ^{e V}DD ^VIL ^{e 0V}
V_DD e 5V
V_DD e 10V
V_DD e 15V
0 05
0 05
0 05
0 0 05
0 0 05
0 0 05
0 05 V
0 05 V
0 05 V
V_OH
l l ^{High Level Output Voltage I}O ^{k 1 mA V}IH ^{e V}DD ^VIL ^{e 0V}
V_DD e 5V
4 95
V_DD e 10V
9 95
V_DD e 15V
14 95
4 95
5
9 95 10
14 95 15
4 95
V
9 95
V
14 95
V
V_IL
l l ^{Low Level Input Voltage I}O ^{k 1 mA}
V_DD e 5V V_O e 0 5V or 4 5V
15
2 25 1 5
15 V
V_DD e 10V V_O e 1V or 9V
30
45 30
30 V
V_DD e 15V V_O e 1 5V or 13 5V
40
6 75 4 0
40 V
V_IH
l l ^{High Level Input Voltage I}O ^{k 1 mA}
V_DD e 5V V_O e 0 5V or 4 5V
35
3 5 2 75
35
V
V_DD e 10V V_O e 1V or 9V
70
70 55
70
V
V_DD e 15V V_O e 1 5V or 13 5V 11 0
11 0 8 25
11 0
V
I_OL
Low Level Output Current V_IH e V_DD V_IL e 0V
(Note 4)
V_DD e 5V V_O e 0 4V
V_DD e 10V V_O e 0 5V
V_DD e 15V V_O e 1 5V
0 52
0 44 0 88
13
1 1 2 25
36
30 88
0 36
mA
09
mA
24
mA
I_OH
High Level Output Current V_IH e V_DD V_IL e 0V
(Note 4)
V_DD e5V V_O e 4 6V
V_DD e 10V V_O e 9 5V
V_DD e15V V_O e 13 5V
b0 52
b0 44 b0 88
b0 36
mA
b1 3
b1 1 b2 25
b0 9
mA
b3 6
b3 0 b8 8
b2 4
mA
I_IN
Input Curent
V_DD e 15V V_IN e 0V
V_DD e 15V V_IN e 15V
b0 3
03
b10^b5 b0 3
10^b5 0 3
b1 0 mA
1 0 mA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 Being a latch the CD4042BM CD4042BC is not clock rise and fall time sensitive
Note 4 I_OH and I_OL are tested one output at a time
3