CD4042BM Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Quad Clocked D Latch

March 1988
CD4042BM CD4042BC Quad Clocked D Latch
General Description
The CD4042BM CD4042BC quad clocked ‘‘D’’ latch is a
monolithic complementary MOS (CMOS) integrated circuit
constructed with P- and N-channel enhancement mode
transistors The outputs Q and Q either latch or follow the
data input depending on the clock level which is pro-
grammed by the polarity input For polarity e 0 the informa-
tion present at the data input is transferred to Q and Q
during 0 clock level and for polarity e 1 the transfer occurs
during the 1 clock level When a clock transition occurs
(positive for polarity e 0 and negative for polarity e 1) the
information present at the input during the clock transition is
retained at the outputs until an opposite clock transition oc-
curs
Features
Y _{Wide supply voltage range}
Y _{High noise immunity}
Y _{Low power TTL}
compatibility
Y _{Clock polarity control}
Y _{Fully buffered data inputs}
Y _{Q and Q outputs}
3 0V to 15V
0 45 V_DD (typ )
Fan out of 2 driving 74L
or 1 driving 74LS
Connection Diagram
Dual-In-Line Package
Truth Table
Clock
0
L
1
K
Polarity
0
0
1
1
Q
D
Latch
D
Latch
Order Number CD4042B
Top View
Logic Diagrams
TL F 5966 – 1
TL F 5966 – 2
C1995 National Semiconductor Corporation TL F 5966
TL F 5966 – 4
TL F 5966 – 3
RRD-B30M105 Printed in U S A