CD4031BM Datasheet, PDF (4/6 Pages) National Semiconductor (TI) – 64-Stage Static Shift Register

AC Electrical Characteristics
T_A e 25 C C_L e 50 pF R_L e 200k Input t_r e t_f e 20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL t_PLH
Propagation Delay Time Clock to Q and Q
V_CC e 5V
V_CC e 10V
V_CC e 15V
300
600
ns
125
250
ns
100
200
ns
t_PHL t_PLH
Propagation Delay Time Clock to CL_D
V_CC e 5V
V_CC e 10V
V_CC e 15V
125
250
ns
60
125
ns
50
100
ns
t_THL t_TLH
Output Transition Time All Outputs
V_CC e 5V
V_CC e 10V
V_CC e 15V
100
200
ns
50
100
ns
40
80
ns
t_SU0
t_SU1
Minimum Data Setup Time DATA IN or
RECIRCULATE IN to Clock
V_CC e 5V
V_CC e 10V
V_CC e 15V
100
200
ns
50
100
ns
40
80
ns
t_H0
Minimum Data Hold Time Clock to DATA IN
V_CC e 5V
t_H1
or RECIRCULATE IN
V_CC e 10V
V_CC e 15V
100
200
ns
50
100
ns
40
80
ns
t_WL t_WH
Minimum Clock Pulse Width
V_CC e 5V
V_CC e 10V
V_CC e 15V
150
30
ns
60
125
ns
50
100
ns
f_CL
Maximum Clock Frequency
V_CC e 5V
16
32
V_CC e 10V
40
80
V_CC e 15V
50
10
MHz
MHz
MHz
t_RCL t_FCL
Maximum Clock Input Rise and Fall Times
V_CC e 5V
15
ms
(Note 4)
V_CC e 10V
10
ms
V_CC e 15V
5
ms
C_IN
Input Capacitance
Any Input
5
75
pF
AC Parameters are guaranteed by DC correlated testing
Note 4 When clocking cascaded packages in parallel one should insure that t_{r CL} s 2 (t_PD b t_H) where t_PD e the propagation delay of the driving stage
and t_H e the hold time of the driven stage
Block Diagram
cascading packages using DELAYED CLOCK (CL_D) output
TL F 5962 – 4
4