CD4031BM Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – 64-Stage Static Shift Register

February 1988
CD4031BM CD4031BC
64-Stage Static Shift Register
General Description
The CD4031BM CD4031BC is an integrated complemen-
tary MOS (CMOS) 64-stage fully static shift register Two
data inputs DATA IN and RECIRCULATE IN and a MODE
CONTROL input are provided Data at the DATA input
(when MODE CONTROL is low) or data at the RECIRCU-
LATE input (when MODE CONTROL is high) which meets
the setup and hold time requirements is entered into the
first stage of the register and is shifted one stage at each
positive transition of the CLOCK
Data output is available in both true and complement forms
from the 64th stage Both the DATA OUT (Q) AND DATA
OUT (Q) outputs are fully buffered
The CLOCK input of the CD4031BM CD4031BC is fully
buffered and present only a standard input load capaci-
tance However a DELAYED CLOCK OUTPUT (CL_D) has
been provided to allow reduced clock drive fan-out and tran-
sition time requirements when cascading packages
Features
Y _{Wide supply voltage range}
3 0V to 15V
Y _{High noise immunity}
Y _{Low power TTL}
compatibility
0 45 V_DD (typ )
fan out of 2 driving 74L
or 1 driving 74LS
Y _{Fully static operation}
Y _{Fully buffered clock input}
DC to 8 MHz
V_DD e 10V (typ )
5 pF (typ )
input capacitance
Y _{Single phase clocking requirements}
Y _{Delayed clock output for reduced clock drive require-}
ments
Y _{Fully buffered outputs}
Y _{High current sinking capability}
1 6 mA
Y _{Q output}
V_DD e 5V and 25 C
Logic and Connection Diagrams
Dual-In-Line Package
TL F 5962 – 1
Order Number CD4031B
Top View
C1995 National Semiconductor Corporation TL F 5962
TL F 5962 – 2
RRD-B30M105 Printed in U S A