ADC08D1020_08 Datasheet, PDF (37/44 Pages) National Semiconductor (TI) – Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh. Note that
when the device is programmed to provide a second DCLK
output, the OR signals become DCLK2. Refer to 1.4 REGIS-
TER DESCRIPTION
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC08D1020 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC08D1020 such that the differential full-scale
input range at the analog inputs is a normal amplitude with
the FSR pin high, or a reduced amplitude with FSR pin low as
defined by the specification V_IN in the Converter Electrical
Characteristics. Best SNR is obtained with FSR high, but bet-
ter distortion and SFDR are obtained with the FSR pin low.
The LMH6555 of is Figure 14 suitable for any Full Scale
Range.
2.3 THE CLOCK INPUTS
The ADC08D1020 has differential LVDS clock inputs, CLK+
and CLK−, which must be driven with an a.c. coupled, differ-
ential clock signal. Although the ADC08D1020 is tested and
its performance is guaranteed with a differential 1 GHz clock,
it typically will function well with input clock frequencies indi-
cated in the Converter Electrical Characteristics. The clock
inputs are internally terminated and biased. The input clock
signal must be capacitively coupled to the clock pins as indi-
cated in Figure 15.
Operation up to the sample rates indicated in the Converter
Electrical Characteristics is typically possible if the maximum
ambient temperatures indicated are not exceeded. Operating
at higher sample rates than indicated for the given ambient
temperature may result in reduced device reliability and prod-
uct lifetime. This is because of the higher power consumption
and die temperatures at high sample rates. Important also for
reliability is proper thermal management . See 2.6.2 Thermal
Management.
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FIGURE 15. Differential (LVDS) Input Clock Connection
The differential input clock line pair should have a character-
istic impedance of 100 Ω and (when using a balun), be
terminated at the clock source in that (100 Ω) characteristic
impedance. The input clock line should be as short and as
direct as possible. The ADC08D1020 clock input is internally
terminated with an untrimmed 100 Ω resistor.
Insufficient input clock levels will result in poor dynamic per-
formance. Excessively high clock levels could cause a
change in the analog input offset voltage. To avoid these
problems, keep the clock level within the range specified as
V_ID in the Converter Electrical Characteristics.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1020 fea-
tures a duty cycle clock correction circuit which can maintain
performance over temperature even in DES mode. The ADC
will meet its performance specification if the input clock high
and low times are maintained within the duty cycle range as
specified in the Converter Electrical Characteristics.
High speed, high performance ADCs such as the AD-
C08D1020 require a very stable input clock signal with mini-
mum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
t_J(MAX) = (V_INFSR / V_IN(P-P)) x (1/(2^(N+1) x π x f_IN))
where t_J(MAX) is the rms total of all jitter sources in seconds,
V_IN(P-P) is the peak-to-peak analog input signal, V_INFSR is the
full-scale range of the ADC, "N" is the ADC resolution in bits
and f_IN is the maximum input frequency, in Hertz, at the ADC
analog input.
Note that the maximum jitter described above is the RSS sum
of the jitter from all sources, including that in the ADC input
clock, that added by the system to the ADC input clock and
input signals and that added by the ADC itself. Since the ef-
fective jitter added by the ADC is beyond user control, the best
the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
Input clock amplitudes above those specified in the Converter
Electrical Characteristics may result in increased input offset
voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
2.4 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the AD-
C08D1020 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Calibration, Calibration Delay,
Output Edge Synchronization choice, LVDS Output Level
choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected with the FSR con-
trol input (pin 14) in the normal mode of operation. The input
full-scale range is specified as V_IN in the Converter Electrical
Characteristics. In the extended control mode, the input full-
scale range may be programmed using the Full-Scale Adjust
Voltage register. See 2.2 THE ANALOG INPUT for more in-
formation.
2.4.2 Calibration
The ADC08D1020 calibration must be run to achieve speci-
fied performance. The calibration procedure is run upon pow-
er-up and can be run any time on command. The calibration
procedure is exactly the same whether there is an input clock
present upon power up or if the clock begins some time after
application of power. The CalRun output indicator is high
while a calibration is in progress. Note that the DCLK outputs
are not active during a calibration cycle by default and there-
fore are not recommended as system clock unless the Re-
sistor Trim Disable feature is used (Reg.9h). The DCLK
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