ADC08D1020_08 Datasheet, PDF (28/44 Pages) National Semiconductor (TI) – Low Power, 8-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

TABLE 2. Input Channel Samples Produced at Data Outputs in Non-Demultiplexed Mode
Data Outputs
(Sourced with
respect to fall
of DCLK+)
Normal Mode
DI
"I" Input Sampled with Fall of CLK 13 cycles earlier.
DId
No output.
DQ
"Q" Input Sampled with Fall of CLK 13 cycles earlier.
DQd
No output.
DES Mode
Selected input sampled 13 cycles earlier.
No output.
Selected input sampled 13.5 cycles earlier.
No output.
1.1.5.2 OutEdge and Demultiplex Control Setting
To help ease data capture in the SDR mode, the output data
may be caused to transition on either the positive or the neg-
ative edge of the output data clock (DCLK). In the non-
extended control mode, this is chosen with the OutEdge input
(pin 4). A high on the OutEdge input pin causes the output
data to transition on the rising edge of DCLK+, while ground-
ing this input causes the output to transition on the falling edge
of DCLK+. See 2.4.3 Output Edge Synchronization. When in
the extended control mode, the OutEdge is selected using the
OED bit in the Configuration Register. This bit has two func-
tions. In the single data rate (SDR) mode, the bit functions as
OutEdge and selects the DCLK edge with which the data
transitions. In the Double Data Rate (DDR) mode, this bit se-
lects whether the device is in non-demultiplex or 1:2 demul-
tiplex mode. In the DDR case, the DCLK has a 0° phase
relationship with the output data independent of the demulti-
plexer selection. For 1:2 Demux DDR 0° Mode, there are four,
as opposed to three cycles of CLK systematic delay from the
Synchronizing Edge to the start of t_OD. See 1.5 MULTIPLE
ADC SYNCHRONIZATIONfor more details.
1.1.5.3 Single Data Rate and Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the output clock
(DCLK) frequency is the same as the data rate of the two out-
put buses. With double data rate the DCLK frequency is half
the data rate and data is sent to the outputs on both edges of
DCLK. DDR clocking is enabled in non-Extended Control
mode by allowing pin 4 to float.
1.1.6 The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are
LVDS. The electrical specifications of the LVDS outputs are
compatible with typical LVDS receivers available on ASIC and
FPGA chips; but they are not IEEE or ANSI communications
standards compliant due to the low +1.9V supply used this
chip. User is given the choice of a lower signal amplitude
mode with OutV control pin or the OV control register bit. For
short LVDS lines and low noise systems, satisfactory perfor-
mance may be realized with the OutV input low, which results
in lower power consumption. If the LVDS lines are long and/
or the system in which the ADC08D1020 is used is noisy, it
may be necessary to tie the OutV pin high.
The LVDS data output have a typical common mode voltage
of 800 mV when the V_BG pin is unconnected and floating. This
common mode voltage can be increased to 1.175V by tying
the V_BG pin to V_A if a higher common mode is required.
IMPORTANT NOTE: Tying the V_BG pin to V_A will also in-
crease the differential LVDS output voltage by up to 40 mV.
1.1.7 Power Down
The ADC08D1020 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
power down mode. In this power down mode the data output
pins (positive and negative) are put into a high impedance
state and the devices power consumption is reduced to a
minimal level. The DCLK+/- and OR +/- are not tri-stated, they
are weakly pulled down to ground internally. Therefore when
both I and Q are powered down the DCLK +/- and OR +/-
should not be terminated to a DC voltage.
A high on the PDQ pin will power down the "Q" channel and
leave the "I" channel active. There is no provision to power
down the "I" channel independently of the "Q" channel. Upon
return to normal operation, the pipeline will contain meaning-
less information.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state. Calibration will
function with the "Q" channel powered down, but that channel
will not be calibrated if PDQ is high. If the "Q" channel is sub-
sequently to be used, it is necessary to perform a calibration
after PDQ is brought low.
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