PC87108AVHG Datasheet, PDF (35/56 Pages) National Semiconductor (TI) – Advanced UART and Infrared Controller

3.0 Architectural Description (Continued)
3.7.1 IRCR3 – Infrared Control Register 3
Used to select the operating mode of the infrared interface.
Upon reset, the content of this register is 20h.
Bits
B7
B6
B5
B4
B3
B2
B1
B0
Function
SHDM__DS SHMD__DS FIR__CRC MIR__CRC res TXCRC__INV TXCRC__DS res
Reset State
0
0
1
0
0
0
0
0
FIGURE 24. Infrared Control Register 3
B0 Reserved.
Write 0.
B1 TXCRC__DS – Disable Transmitter CRC.
When set to 1, a CRC is not transmitted.
B2 TXCRC__INV – Invert Transmitter CRC.
When set to 1, an inverted CRC is transmitted. This bit can be used to force a bad CRC for testing purposes.
B3 Reserved.
Write 0.
B4 MIR__CRC – MIR Mode CRC Select.
Determines the length of the CRC in MIR mode.
0 → 16-bit CRC
1 → 32-bit CRC
B5 FIR__CRC – FIR Mode CRC Select.
Determines the length of the CRC in FIR mode.
0 → 16-bit CRC
1 → 32-bit CRC
B6 SHMD__DS – Sharp-IR Modulation Disable.
When set to 1, internal 500 kHz transmitter modulation is disabled.
B7 SHDM__DS – Sharp-IR Demodulation Disable.
When set to 1, internal 500 kHz receiver demodulation is disabled.
3.7.2 MIR__PW – MIR Pulse Width Register
This register is used to program the width of the transmitted MIR infrared pulses in increments of either 20.833 ns or 41.666 ns
depending on the setting of the MDSR bit in the IRCR2 register. The programmed value has no effect on the MIR receiver. After
reset, the content of this register is 0Ah.
Bits
B7
B6
B5
B4
B3
B2
Function
res
res
res
res
MPW3
MPW2
Reset State
0
0
0
0
1
0
FIGURE 25. MIR Pulse Width Register
B3-0 MPW [3–0] – MIR Signal Pulse Width
Encoding
00XX
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Pulse Width, MDRS = 0
Reserved
83.33 ns
104.16 ns
125 ns
145.83 ns
166.66 ns
187.50 ns
208.33 ns
229.16 ns
250 ns
270.83 ns
Pulse Width, MDRS = 1
Reserved
166.66 ns
208.33 ns
250 ns
291.66 ns
333.33 ns
374.99 ns
416.66 ns
458.33 ns
500 ns
541.66 ns
B1
MPW1
1
B0
MPW0
0
35
www.national.com