PC87108AVHG Datasheet, PDF (24/56 Pages) National Semiconductor (TI) – Advanced UART and Infrared Controller

3.0 Architectural Description (Continued)
B7 DCD – Data Carrier Detect.
This bit returns the complement of the DCD input.
3.1.8 SPR/ASCR – Scratchpad/Auxiliary Status and Control Register
These registers share the same address.
SPR– Scratchpad Register.
This register is accessed when the device is in non-extended mode.
It does not control the device in any way, and is intended to be used by the programmer to hold data temporarily.
ASCR– Auxiliary Status and Control Register.
This register is accessed when the extended mode of operation is selected.
All the ASCR bits are cleared when a hardware reset occurs or when the operational mode changes.
Bits 2 and 6 are cleared when the transmitter is soft reset.
Bits 0, 1, 4 and 5 are cleared when the receiver is soft reset.
The format of ASCR is shown in Figure 14.
Bits
Function
Reset State
B7
PLD/
CTE
0
B6
TXUR
0
B5
RXBSY/
RXACT
0
B4
LOST__FR/
RXWDG
0
B3
B2
B1
B0
TXHFE S__EOT FEND__INF RXF__TOUT
0
0
0
0
FIGURE 14. Auxiliary Status and Control Register
B0
RXF__TOUT – RX__FIFO Time-out.
This bit is read-only, and is set to 1 when an RX__FIFO time-out occurs.
In MIR or FIR modes this bit can be used in conjunction with bit 1 to determine whether a number of bytes, as deter-
mined by the RX__FIFO threshold, can be read without checking the RXDA bit in the LSR register for each byte.
Cleared when a character is read from the RX__FIFO.
B1
MIR, FIR Modes
FEND__INF – Frame End Bytes in RX__FIFO.
This bit is read-only, and is set to 1 when one or more Frame End bytes are in the RX__FIFO.
Cleared when no Frame End byte is in the RX__FIFO.
B2
MIR, FIR Modes
S__EOT – Set End of Transmission.
When a 1 is written into this bit position before writing the last character into the TX__FIFO, frame transmission is com-
pleted and a CRC + EOF is sent. This bit can be used as an alternative to the Transmitter Frame Length register. If
this method is to be used, the FEND__MD bit in the IRCR2 register should be set to 1, or the Transmitter Frame
Length register should be set to maximum count.
This bit is automatically cleared by the hardware when a character is written into the TX__FIFO.
CEIR Mode
S__EOT – Set End of Transmission.
When a 1 is written into this bit position before writing the last character into the TX__FIFO, data transmission is grace-
fully completed. If the CPU simply stops writing data into the TX__FIFO at the end of the data stream, a transmitter
underrun is generated and the transmitter stops. In this case, this is not an error, however the software needs to clear
the underrun before the next transmission can occur.
This bit is automatically cleared by the hardware when a character is written into the TX__FIFO.
B3
MIR, FIR Modes
TXHFE – Transmitter Halted on Frame End.
This bit is used only when the transmitter frame-end stop mode is selected (TX__MS bit in IRCR2 set to 1). It is set
to 1 by the hardware when transmission of a frame is complete and the end-of-frame condition was generated by the
TFRCC counter reaching 0.
This bit must be cleared, by writing 1 into it, to re-enable transmission.
B4
MIR, FIR Modes
LOST__FR – Lost Frame Flag.
This bit is read-only, and reflects the setting of the lost-frame indicator flag at the bottom of the ST__FIFO.
CEIR Mode
RXWDG – Receiver Watch Dog.
www.national.com
24