CR16HCS5 Datasheet, PDF (35/156 Pages) National Semiconductor (TI) – Family of 16-bit CAN-enabled CompactRISC Microcontrollers

10.4.7 Interrupt Status Register 1 (ISTAT1)
The ISTAT1 register is a word-wide, read-only register that
indicates which maskable interrupt inputs to the ICU31L
(IRQ16 through IRQ31) are currently active. The register for-
mat is shown below.
15
0
IST(31:16)
IST(31:16)
Interrupt Status bits. Each bit indicates the cur-
rent status of an interrupt input to the ICU31L,
corresponding to interrupts IRQ16 through
IRQ31. A bit set to 1 indicates an active inter-
rupt input, even when the interrupt is masked
out by the IENAM0 register. A bit cleared to 0
indicates an inactive interrupt input.
10.4.8 Interrupt Debug Register
The IDBG register is a word-wide read-only register, which
contains various status information of the ICU31L. The low-
est 6 bits contain the INTVECT value during the last read
from address FE00. The next 6 bits contain the INTVECT
value when a maskable interrupt request is sent to the
CR16B core. Upon reset, this register is set to 0000 hex.
10.5 INTERRUPT PROGRAMMING
PROCEDURES
The following subsections provide information on initializing
the device for interrupts, clearing interrupts, and nesting in-
terrupts.
10.5.1 Initialization
Upon reset, all interrupts are disabled. To program the device
for interrupt operation and to enable interrupts, use the fol-
lowing procedure in the application software:
1. Set the Interrupt Stack Pointer (ISP)
2. Load the INTBASE register so that it points to the base
of the Interrupt Dispatch Table.
3. Perform any required preparation steps for the interrupt
service routines.
4. Initialize the peripheral devices that can generate inter-
rupts and set their respective interrupt enable bits.
5. Set the relevant bits in the interrupt mask registers
(IENAM0 and IENAM1)
Note: The MIWU16 interrupts have no local interrupt en-
able bits, which means you can only disable the
MIWU16 interrupts if you clear the specific bits in the IE-
NAM register.
6. Use the Load Processor Register (LPR) instruction to
set I bit in the PSR register.
7. When the device is ready to execute interrupts, set the
E bit in the PSR register by executing the Enable Inter-
rupts (EI) instruction.
Once maskable interrupts are enabled by setting the E and I
bits, you can disable and re-enable all maskable interrupts
locally by using the Enable Interrupts (EI) and Disable Inter-
rupts (DI) instructions, which set and clear the E bit.
10.5.2 Clearing Interrupts
Clearing an interrupt request before it is serviced may cause
a spurious interrupt because the CPU may detect an inter-
rupt not reflected in the Interrupt Vector (IVCT) register. To
ensure reliable operation, clear interrupt requests only while
interrupts are disabled.
Changing the polarity of an interrupt input (for example, in the
Multi-Input Wake-Up module) can cause a spurious interrupt,
and therefore should be done only while interrupts are dis-
abled.
For the same reason, clearing an enable bit in a peripheral
module should be carried out only while the interrupt is dis-
abled.
10.5.3 Nesting Interrupts
Interrupts may be nested, or in other words, an interrupt ser-
vice routine can itself be interrupted by a different interrupt
source. There is no hardware limitation on the number of in-
terrupt nesting levels. However, the interrupt stack must not
be allowed to overflow its allocated memory space.
Unless specifically enabled by the software, nested inter-
rupts will not occur. When the CPU acknowledges an inter-
rupt, the I bit in the PSR register is automatically cleared to 0
for the duration of the service routine, disabling any further
maskable interrupts.
To allow nested interrupts, an interrupt service routine should
first set or clear the respective interrupt enable bits to specify
which peripherals will be allowed to interrupt the current ser-
vice routine. The present interrupt routine should be disabled
(or interrupt pending bit cleared). The service routine should
then set the PSR.I bit to 1, thus enabling maskable interrupts.
This bit can be controlled with the Store Processor Register
(SPR) and Load Processor Register (LPR) instructions.
Note:
Clearing the pending bit of the current interrupt should not be
immediately followed by enabling further interrupts by setting
the I bit in the PSR register. Wait states must be inserted into
the software after clearing the interrupt pending bit and be-
fore another interrupt. Placing a NOP instruction will perform
this instruction. This is because the instruction which resets
the pending bit may not yet be finished when the interrupts
are already enabled again by setting the I bit in the PSR reg-
ister. To avoid this situation the user has to make sure that
prior to enabling the interrupt an additional instruction is in-
serted. This could look like the example below:
SBITi $0, T1ICRL # clear pending bit
NOP
# NOP instruction
MOVW $0x0a00, r0 # enable further interrupts
LPR r0, psr
A CBITi or SBITi instruction may be used to clear the interrupt
pending bit. In such cases, a spurious interrupt may occur.
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