CR16HCS5 Datasheet, PDF (1/156 Pages) National Semiconductor (TI) – Family of 16-bit CAN-enabled CompactRISC Microcontrollers

January 2002
CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5
CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9
Family of 16-bit CAN-enabled CompactRISC
Microcontrollers
1.0 General Description
The family of 16-bit CompactRISC™ microcontroller is
based on a Reduced Instruction Set Computer (RISC) ar-
chitecture. The device operates as a complete microcom-
puter with all system timing, interrupt logic, flash program
memory or ROM memory, RAM, EEPROM data memory,
and I/O ports included on-chip. It is ideally suited to a wide
range of embedded controller applications because of its
high performance, on-chip integrated features and low
power consumption resulting in decreased system cost.
The device offers the high performance of a RISC architec-
ture while retaining the advantages of a traditional Com-
plex Instruction Set Computer (CISC): compact code, on-
chip memory and I/O, and reduced cost. The CPU uses a
three-stage instruction pipeline that allows execution of up
to one instruction per clock cycle, or up to 25 million in-
structions per second (MIPS) at a clock rate of 24 MHz.
The device contains a FullCAN class, CAN serial interface
for low/high speed applications with 15 orthogonal mes-
sage buffers, each supporting standard as well as extend-
ed message identifiers.
Block Diagram
CR16B
RISC Core
Processing
Unit
Core Bus
Fast Clk Slow Clk*
Clock Generator
Power-on-Reset
CR16CAN
FullCAN 2.0B
Peripheral
Bus
Controller
64k-Byte
Flash
Program
Memory
3k-Byte
RAM
2176-Byte
EEPROM
Data
Memory
1.5k-Byte
ISP
Memory
Interrupt
Control
Power
Manage-
ment
Timing and
Watchdog
Peripheral Bus
I/O
µWire/SPI
2x
USART
ACCESS
bus
4x
VTU
2x
12-ch
MFT 8-bit A/D
MIWU
2 Analog
Comparators
Please note that not all family members contain same peripheral modules and features.
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