USBN9602 Datasheet, PDF (34/45 Pages) National Semiconductor (TI) – USBN9602 (Universal Serial Bus) Full Speed Function Controller With DMA Support

11.0 Register Set (Continued)
11.34 Receive Data Register x (RXD1, RXD2,
RXD3)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
RXFD
–
r
The Receive Data Registers RXD1, RXD2, and RXD3
hold data from Receive Endpoint FIFOs 2, 4, and 6, re-
spectively. The three registers follow the format shown
above.
11.34.1 RXFD
Receive FIFO Data Byte. See “Receive Endpoint FIFO
Operation (RXFIFO1, RXFIFO2, RXFIFO3)” on page 20
for a description of Endpoint FIFO data handling.
The firmware should expect to read only the packet pay-
load data. The PID and CRC16 are removed automatically
by the receive state machine.
34
www.national.com