USBN9602 Datasheet, PDF (32/45 Pages) National Semiconductor (TI) – USBN9602 (Universal Serial Bus) Full Speed Function Controller With DMA Support

11.0 Register Set (Continued)
11.30 Transmit Command Register x (TXC1,
TXC2, TXC3)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
IGN_ISOMSK TFWL[1:0] res FLUSH TOGGLE LAST TX_EN
0
00– 0
0
00
r/w
r/w
– r/w r/w r/w r/w
HW
HW HW
The Transmit Command Registers TXC1, TXC2, and
TXC3 allow control of Transmit Endpoint FIFOs 2, 4, and
6, respectively. The three registers follow the format
shown above.
11.30.5 TFWL
Transmit FIFO Warning Limit. These bits specify how
many more bytes can be transmitted from the correspond-
ing FIFO before an underrun condition occurs. If the num-
ber of bytes remaining in the FIFO is equal or less than
the selected warning limit, the WARN bit within the FIFO
Warning Event Register (FWEV.TXFW[x]) is set. To avoid
interrupts caused by setting the TXFW[x] bit while the
FIFO is filled before a transmission is started, the TXF-
WL[x] bit is only set when transmission from the endpoint
is enabled (TXC[x].TX_EN is set). See Table 6.
Table 6. Transmit FIFO Warning Limits
TFWL[1:0]
Transmit WARN Condition
11.30.1 TX_EN
0 0 Disable WARN warning bit for transmit FIFOs
Transmit Enable. This bit must be set by the firmware to _{0 1 ≤ 4 bytes left in FIFO to transmit}
start a packet transmission. It is cleared by the chip after
transmitting a single packet or a STALL handshake in re- 1 0 ≤ 8 bytes left in FIFO to transmit
sponse to an IN token. If the TXSx.TX_DONE bit is set,
this bit is prevented from being set.
1
1 ≤ 16 bytes left in FIFO to transmit
11.30.2 LAST
Last Byte. Setting this bit indicates to the chip that the en-
tire packet has been written into the FIFO. This is used
especially for streaming data to the FIFO during the actual
transmission. If the LAST bit is not set and the transmit
FIFO becomes empty during a transmission, a stuff error
followed by an EOP is forced on the bus. A zero-length
packet is indicated by setting this bit without writing any
data into the FIFO.
The transmit state machine transmits the payload data,
CRC16, and EOP signal, and then clears the LAST bit.
11.30.3 TOGGLE
Data Toggle. This bit has two functions: one for the ISO
mode (EPCx.ISO bit set) and one for the non-ISO mode
(EPCx.ISO bit cleared).
For non-ISO operation, the bit specifies the type of PID
used for transmitting the packet. A value of 0 causes a
DATA0 PID to be generated, while a value of 1 causes a
DATA1 PID to be generated.
For ISO mode of operation, this bit and the least signifi-
cant bit of the frame counter (FNL[0]) act as a mask for
the TX_EN bit to allow pre-queueing of packets to specific
frame numbers. In other words, transmission in ISO mode
is only enabled if FNL[0] = TOGGLE. If an IN token is not
received while this condition is true, the contents of the
FIFO are flushed with the next SOF. If the endpoint is set
to ISO, data is always transferred with a DATA0 PID.
11.30.6 IGN_ISOMSK
Ignore ISO mask. This bit only has an effect if the end-
point is set to be isochronous. If set, this bit disables lock-
ing to specific frame numbers with the alternate function
of the TOGGLE bit. Thus, data is transmitted upon recep-
tion of the next IN token. If IGN_ISOMSK is cleared, data
is only transmitted when FNL[0] matches TOGGLE.
11.31 Transmit Data Register x (TXD1, TXD2,
TXD3)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
TXFD
don’t care
w
The Transmit Data Registers TXD1, TXD2, and TXD3
hold data for Transmit Endpoint FIFOs 2, 4, and 6, respec-
tively. The three registers follow the format shown above.
11.31.1 TXFD
Transmit FIFO Data Byte. See “Transmit Endpoint FIFO
Operation (TXFIFO1, TXFIFO2, TXFIFO3)” on page 19 for
a description of Endpoint FIFO data handling.
The firmware is expected to write only the packet payload
data. The PID and CRC16 are inserted automatically in
the transmitted data stream.
This bit is not altered by the hardware.
11.30.4 FLUSH
Flush FIFO. Writing a 1 to this bit flushes all data from the
corresponding transmit FIFO, resets the Endpoint to IDLE,
and clears both the FIFO read and write pointers. If the
MAC is currently using the FIFO to transmit, data flushing
is delayed until after the transmission is done.
32
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