LP39542 Datasheet, PDF (32/58 Pages) National Semiconductor (TI) – Advanced Lighting Management Unit

Logic Interface Electrical Characteristics
(1.65V ≤ V_DDIO ≤ V_DD1,2V) (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
LOGIC INPUTS ADDR_SEL, NRST, SCL, SYNC_PWM, FLASH_EN, SDA
V_IL
Input Low Level
V_IH
Input High Level
I_L
Logic Input Current
f_SCL
Clock Frequency
LOGIC OUTPUT SDA
0.8×V_DDIO
−1.0
V_OL
Output Low Level
I_SDA = 3 mA
I_L
Output Leakage Current V_SDA = 2.8V
Typ
Max
0.2×V_DDIO
1.0
400
0.3
0.5
1.0
Note: Any unused digital input pin has to be connected to GND to avoid floating and extra current consumption.
Units
V
V
μA
kHz
V
μA
I²C Compatible Interface
INTERFACE BUS OVERVIEW
The I²C compatible synchronous serial interface provides ac-
cess to the programmable functions and registers on the
device. This protocol uses a two-wire interface for bi-direc-
tional communications between the devices connected to the
bus. The two interface lines are the Serial Data Line (SDA),
and the Serial Clock Line (SCL). These lines should be con-
nected to a positive supply, via a pull-up resistor and remain
HIGH even when the bus is idle. Every device on the bus is
assigned a unique address and acts as either a Master or a
Slave depending on whether it generates or receives the se-
rial clock (SCL).
DATA TRANSACTIONS
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (SCL). Con-
sequently, throughout the clock’s high period, the data should
remain stable. Any changes on the SDA line during the high
state of the SCL and in the middle of a transaction, aborts the
current transaction. New data should be sent during the low
SCL state. This protocol permits a single data line to transfer
both command/control information and data using the syn-
chronous serial clock.
I²C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I²C master always generates
START and STOP bits. The I²C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I²C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
30008550
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9^th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
After the START condition, the I²C master sends a chip ad-
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP39542 address
is 54h or 55H as selected with ADDR_SEL pin. I²C address
for LP39542 is 54H when ADDR_SEL=0 and 55H when
ADDR_SEL=1. For the eighth bit, a “0” indicates a WRITE
and a “1” indicates a READ. The second byte selects the reg-
ister to which the data will be written. The third byte contains
data to write to the selected register.
I²C Signals: Data Validity
30008549
I²C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I²C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
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I²C Chip Address
30008551