LP3905 Datasheet, PDF (3/15 Pages) National Semiconductor (TI) – Power Management Unit For Low Power Handheld Applications

Connection Diagram (Continued)
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DAP
Name
EN2
TGND
LDO2
VIN2
LDO1
GND
EN1
FB1
GND_B1
SW1
VIN1
SW2
GND_B2
FB2
SGND
Description
Enable Pin for Buck2
Ground Pin
LDO2 Output Pin
Input Power Terminal to LDO1 & 2
LDO1 Output Pin
LDO1 & 2 Ground Pin
Enable Pin for Buck1 and LDO1&2
Buck1 Feedback Pin
Buck1 Ground Pin
Buck1 Switch Pin
Input Power Terminal to Buck1 & 2
Buck2 Switch Pin
Buck2 Ground Pin
Buck2 Feedback Pin
Die Attach Pad (DAP)
Package Marking Diagram
20152905
• The physical placement of the package marking will vary from part to part.
• Date Code - UZXYTT format. ’U’ - Wafer fab code; ’Z’ - assembly site code; ’XY’ 2 digit date code; ’TT’ die run code
• See National Web site for more info - http://www.national.com/quality/marking_conventions.html
FIGURE 4. LP3905 14 Pin LLP Package Marking
NS package number SDA14B
Ordering Information
Buck 1 [V] Buck 2 [V] LDO 1 [V] LDO 2 [V] Order Number
1.2
1.875
2.8
2.8 LP3905SD-00
LP3905SDX-00
1.2 Fixed 1.875
2.8
2.8 LP3905SD-30
PWM
Fixed
PWM
LP3905SDX-30
ADJ
ADJ
3.0
2.8 LP3905SD-A3
LP3905SDX-A3
Package Marking
3905-00
3905-30
Supplied As
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
3905-A3
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
3
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