LP3905 Datasheet, PDF (14/15 Pages) National Semiconductor (TI) – Power Management Unit For Low Power Handheld Applications

LP3905 Board Layout
Considerations
PC board layout is an important part of DC-DC converter
design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to
EMI, ground bounce, and resistive voltage loss in the traces.
These can send erroneous signals to the DC-DC converter
IC, resulting in poor regulation or instability.
Good layout for the LP3905 can be implemented by follow-
ing a few simple design rules.
1. Place the Buck inductor and filter capacitors close
together and make the traces short. The traces between
these components carry relatively high switching cur-
rents and act as antennas. Following this rule reduces
radiated noise. Special care must be given to place the
input filter capacitor very close to the V_IN and GND pin.
2. Arrange the components so that the switching current
loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor
through the LP3905 and inductor to the output filter
capacitor and back through ground, forming a current
loop. In the second half of each cycle, current is pulled
up from ground through the LP3905 by the inductor to
the output filter capacitor and then back through ground
forming a second current loop. Routing these loops so
the current curls in the same direction prevents mag-
netic field reversal between the two half-cycles and re-
duces radiated noise.
3. Connect the ground pins of the Bucks and filter capaci-
tors together using generous component-side copper fill
as a pseudo-ground plane. Then, connect this to the
ground-plane (if one is used) with several vias. This
reduces ground-plane noise by preventing the switching
currents from circulating through the ground plane. It
also reduces ground bounce at the LP3905 by giving it a
low-impedance ground connection.
4. Use wide traces between the power components and for
power connections to the DC-DC converter circuit. This
reduces voltage errors caused by resistive losses across
the traces.
5. Route noise sensitive traces, such as the voltage feed-
back path, away from noisy traces between the power
components. The voltage feedback trace must remain
close to the Buck circuits and should be direct but should
be routed opposite to noisy components. This reduces
EMI radiated onto the DC-DC converter’s own voltage
feedback trace. A good approach is to route the feed-
back trace on another layer and to have a ground plane
between the top layer and layer on which the feedback
trace is routed. In the same manner for the adjustable
part it is desired to have the feedback dividers on the
bottom layer.
6. Place noise sensitive circuitry, such as radio IF blocks,
away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-
sensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to
place the DC-DC converters on one corner of the board,
arrange the CMOS digital circuitry around it (since this also
generates noise), and then place sensitive preamplifiers and
IF stages on the diagonally opposing corner. Often, the
sensitive circuitry is shielded with a metal pan and power to
it is post-regulated to reduce conducted noise, using low-
dropout linear regulators.
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