DS99R124Q Datasheet, PDF (3/24 Pages) National Semiconductor (TI) – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

Pin Name
Pin #
I/O, Type Description
LVCMOS Outputs
OS[2:0]
10, 11, 12 O, LVMOS
Over-Sampled Low Frequency Outputs
These bits map to the DS99R421's OS[2:0] over-sampled low-frequency inputs. Signals
must be slower the TxCLK/5. On the DS90UR241 these map to the DIN[23:21] inputs. OS0
= DIN21, OS1 = DIN22, OS2 = DIN23.
LOCK
27
O, LVMOS LOCK Status Output
LOCK = 1, PLL is locked, outputs are active.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL.
Maybe used as a Link Status or to flag when the Video Data is active (ON/OFF).
Control and Configuration
PDB
1
I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down, the output are controlled by the settings. Control registers
are RESET.
VODSEL
33
I, LVCMOS
w/ pull-down
Differential Driver Output Voltage Select
VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
SeeTable 2
OEN
34
I, LVCMOS Output Enable Input
w/ pull-down OEN = 1, FPD-Link outputs are enabled (active).
OEN = 0, FPD-Link outputs are TRI-STATE.
OSS_SEL
35
I, LVCMOS Output Sleep State Select Input
w/ pull-down See Table 1
LFMODE
36
I, LVCMOS Low Frequency Mode — Pin or Register Control
w/ pull-down LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20-43 MHz)
SSC[2:0]
7, 2, 3
I, LVCMOS Spread Spectrum Clock Generation (SSCG) Range Select
w/ pull-down SeeTable 3 and Table 4
RES[1:0]
37, 15
I, LVCMOS Reserved
w/ pull-down Tie Low
Control and Configuration — STRAP PIN
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon
power-up and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket.
EQ
28 [PASS] STRAP
EQ Gain Control of FPD-Link II Input
I, LVCMOS EQ = 1, EQ gain is enabled (~13 dB)
w/ pull-down EQ = 0, EQ gain is disabled (~1.625 dB)
Optional BIST Mode
BISTEN
29
I, LVCMOS BIST Enable Input – Optional
w/ pull-down BISTEN = 1, BIST Mode is enabled.
BISTEN = 0, normal mode.
BISTM
30
I, LVCMOS BIST Mode Input – Optional
w/ pull-down BISTM = 1, selects Payload Error Mode
BISTM = 0, selects Pass / Fail Result-Only Mode
PASS
28
O, LVCMOS PASS Output (BIST Mode) – Optional
PASS = 1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control Interface
SCL
5
I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
SDA
4
I/O,
Serial Control Bus Data Input / Output - Optional
LVCMOS SDA requires an external pull-up resistor to V_DDIO.
Open Drain
3
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