DS99R124Q Datasheet, PDF (17/24 Pages) National Semiconductor (TI) – 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

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FIGURE 17. BIST Mode Flow Diagram
Sample BIST Sequence
SeeFigure 17 for the BIST mode flow diagram.
Step 1: For the DS99R421 FPD-Link II Ser BIST Mode is en-
abled via the BISTEN pin. For the DS90UR241 Ser, BIST
mode is enetered by setting all the input data of the device to
Low state. A PCLK is required for all the Ser options. When
the Des detects the BIST mode pattern and command (DCA
and DCB code) the RGB and control signal outputs are shut
off.
Step 2: Place the DS99R124Q Des in BIST mode by setting
the BISTEN = H. The Des is now in the BIST mode. If BISTM
= H, the Des will check the incoming serial payloads for errors.
If an error in the payload (1 to 24) is detected, the PASS pin
will switch low for one half of the clock period. During the BIST
test, the PASS output can be monitored and counted to de-
termine the payload error rate.
Step 3: To Stop the BIST mode, the Des BISTEN pin is set
Low. The Des stops checking the data. The final test result is
held on the PASS pin. If the test ran error free, the PASS
output will be High. If there was one or more errors detected,
the PASS output will be Low. The PASS output state is held
until a new BIST is run, the device is RESET, or Powered
Down. The BIST duration is user controlled by the duration of
the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN
input is set Low. The Link returns to normal operation.
Figure 18 shows the waveform diagram of a typical BIST test
for two cases. Case 1 is error free, and Case 2 shows one
with multiple errors. In most cases it is difficult to generate
errors due to the robustness of the link (differential data trans-
mission etc.), thus they may be introduced by greatly extend-
ing the cable length, faulting the interconnect, reducing signal
condition enhancements (De-Emphasis, VODSEL, or Rx
Equalization).
FIGURE 18. BIST Waveforms
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