DS90CF366_06 Datasheet, PDF (3/16 Pages) National Semiconductor (TI) – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85MHz

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
RECEIVER SUPPLY CURRENT
(Figures 2, 3, 4 )
f = 65 MHz
f = 85 MHz
ICCRZ Receiver Supply Current
Power Down = Low
Power Down
Receiver Outputs Stay Low during
Power Down Mode
Min Typ Max Units
43
60
mA
43
70
mA
140 400
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_OD and ∆V _OD).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4 )
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 11, f = 85 MHz
0.49
Figure 12 )
RSPos1 Receiver Input Strobe Position for Bit 1
2.17
RSPos2 Receiver Input Strobe Position for Bit 2
3.85
RSPos3 Receiver Input Strobe Position for Bit 3
5.53
RSPos4 Receiver Input Strobe Position for Bit 4
7.21
RSPos5 Receiver Input Strobe Position for Bit 5
8.89
RSPos6 Receiver Input Strobe Position for Bit 6
10.57
RSKM
RxIN Skew Margin (Note 4) (Figure 13 )
f = 85 MHz
290
RCOP
RxCLK OUT Period (Figure 5)
11.76
RCOH RxCLK OUT High Time (Figure 5 )
f = 85 MHz
4.5
RCOL
RxCLK OUT Low Time (Figure 5)
4.0
RSRC
RxOUT Setup to RxCLK OUT (Figure 5 )
2.0
RHRC
RxOUT Hold to RxCLK OUT (Figure 5 )
3.5
RCCD
RxCLK IN to RxCLK OUT Delay @ 25˚C, V_CC = 3.3V (Figure 6 )
5.5
RPLLS Receiver Phase Lock Loop Set (Figure 7 )
RPDD
Receiver Power Down Delay (Figure 10 )
Typ
2.0
1.8
0.84
2.52
4.20
5.88
7.56
9.24
10.92
T
5
5
7.0
Max
Units
3.5
ns
3.5
ns
1.19
ns
2.87
ns
4.55
ns
6.23
ns
7.91
ns
9.59
ns
11.27
ns
ps
50
ns
7
ns
6.5
ns
ns
ns
9.5
ns
10
ms
1
µs
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).
3
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