DS90CF366_06 Datasheet, PDF (10/16 Pages) National Semiconductor (TI) – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 9) + ISI (Inter-symbol interference) (Note 10)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 9: Cycle-to-cycle jitter is less than 250 ps at 85 MHz.
Note 10: ISI is dependent on interconnect length; may be zero.
FIGURE 13. Receiver LVDS Input Skew Margin
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