DS90CF366_06 Datasheet, PDF (11/16 Pages) National Semiconductor (TI) – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-85MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-85MHz

DS90CF386 MTD56 Package Pin Descriptions—24-Bit FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O
No.
I
4
I
4
O
28
I
1
I
1
O
1
I
1
I
4
I
5
I
1
I
2
I
1
I
3
Description
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control
lines — FPLINE, FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data
Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
DS90CF366 MTD48 Package Pin Descriptions—18-Bit FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O No.
I3
I3
O 21
I1
I1
O1
I1
I4
I5
I1
I2
I1
I3
Description
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
DS90CF386 — 64 ball FBGA package Pin Descriptions —
FPD Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
FPSHIFT OUT
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
I/O No.
I4
I4
O 28
I1
I1
O1
I1
I4
I5
I1
I2
I1
Description
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
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