CD4023BM Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Buffered Triple 3-Input NAND,NOR Gate

DC Electrical Characteristics CD4023BC CD4025BC (Note 2)
Symbol
Parameter
Conditions
b40 C
a25 C
a85 C _Units
Min Typ Min Typ Max Min Max
I_DD
Quiescent Device Current V_DD e 5V
V_DD e 10V
V_DD e 15V
10
0 004 1 0
7 5 mA
20
0 005 2 0
15 mA
40
0 006 4 0
30 mA
V_OL Low Level Output Voltage V_DD e 5V
V_DD e 10V
V_DD e 15V
0 05
0 0 05
0 05 V
0 05
0 0 05
0 05 V
0 05
0 0 05
0 05 V
V_OH
High Level Output Voltage V_DD e 5V
V_DD e 10V
V_DD e 15V
4 95
9 95
14 95
4 95 5
9 95 10
14 95 15
4 95
V
9 95
V
14 95
V
V_IL
Low Level Input Voltage
( ^{l l VDDe5V VOe4 5V}
V_DDe10V V_Oe9 0V
V_DDe15V V_Oe13 5V
I_O ^k1mA
15
30
40
2 15
4 30
6 40
15 V
30 V
40 V
V_IH
High Level Input Voltage
( ^{l l VDDe5V VOe0 5V}
V_DDe10V V_Oe1 0V
V_DDe15V V_Oe1 5V
I_O ^k1mA
35
70
11 0
35
3
70
6
11 0 9
35
V
70
V
11 0
V
I_OL
Low Level Output Current V_DDe5V V_O e 0 4V
(Note 3)
V_DD e 10V V_O e 0 5V
V_DD e 15V V_O e 1 5V
0 52
0 44 0 88
13
11 22
36
30
8
0 36
mA
0 90
mA
24
mA
I_OH
High Level Output Current V_DD e 5V V_O e 4 6V
(Note 3)
V_DD e 10V V_O e 9 5V
V_DD e 15V V_O e 13 5V
b0 52
b0 44 b0 88
b0 36
mA
b1 3
b1 1 b2 2
b0 90
mA
b3 6
b3 0 b8
b2 4
mA
I_IN
Input Current
V_DD e 15V V_IN e 0V
V_DD e 15V V_IN e 15V
b0 3
03
b10^b5 b0 3
10^b5 0 3
b1 0 mA
1 0 mA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 I_OH and I_OL are tested one output at a time
Schematic Diagram
CD4025BM CD4025BC
Device Shown
All Inputs Protected
by Standard CMOS Input
Protection Circuit
TL F 5956 – 4
3