CD4023BM Datasheet, PDF (2/6 Pages) National Semiconductor (TI) – Buffered Triple 3-Input NAND,NOR Gate

Absolute Maximum Ratings (Notes 1 2)
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DC Supply Voltage (V_DD)
Input Voltage (V_IN)
Storage Temp Range (T_S)
Power Dissipation (P_D)
Dual-In-Line
Small Outline
b0 5 V_DC to a18 V_DC
b0 5 V_DC to V_DDa0 5 V_DC
b65 C to a150 C
700 mW
500 mW
Lead Temperature (T_L)
(Soldering 10 seconds)
260 C
Recommended Operating
Conditions
DC Supply Voltage (V_DD)
Input Voltage (V_IN)
Operating Temperature Range (T_A)
CD4023BM CD4025BM
CD4023BC CD4025BC
5 V_DC to 15 V_DC
0 V_DC to V_DD V_DC
b55 C to a125 C
b40 C to a85 C
DC Electrical Characteristics CD4023BM CD4025BM (Note 2)
Symbol
Parameter
Conditions
b55 C
a25 C
a125 C _Units
Min Typ Min Typ Max Min Max
I_DD
Quiescent Device Current V_DD e 5V
V_DD e 10V
V_DD e 15V
0 25
0 004 0 25
7 5 mA
05
0 005 0 5
15 mA
10
0 006 1 0
30 mA
V_OL Low Level Output Voltage V_DD e 5V
V_DD e 10V
V_DD e 15V
0 05
0 0 05
0 05 V
0 05
0 0 05
0 05 V
0 05
0 0 05
0 05 V
V_OH
High Level Output Voltage V_DD e 5V
V_DD e 10V
V_DD e 15V
4 95
9 95
14 95
4 95 5
9 95 10
14 95 15
4 95
V
9 95
V
14 95
V
V_IL
Low Level Input Voltage
( ^{l l VDDe5V VOe4 5V}
V_DDe10V V_Oe9 0V
V_DDe15V V_Oe13 5V
I_O ^k1mA
15
30
40
2
15
4
30
6
40
15 V
30 V
40 V
V_IH
High Level Input Voltage
( ^{l l VDDe5V VOe0 5V}
V_DDe10V V_Oe1 0V
V_DDe15V V_Oe1 5V
35
I_O ^k1mA 7 0
11 0
I_OL
Low Level Output Current V_DDe5V V_O e 0 4V
(Note 3)
V_DD e 10V V_O e 0 5V
V_DD e 15V V_O e 1 5V
0 64
16
42
35
3
70
6
11 0 9
0 51 0 88
13 22
34
8
35
V
70
V
11 0
V
0 36
mA
0 90
mA
24
mA
I_OH
High Level Output Current V_DD e 5V V_O e 4 6V
(Note 3)
V_DD e 10V V_O e 9 5V
V_DD e 15V V_O e 13 5V
I_IN
Input Current
V_DD e 15V V_IN e 0V
V_DD e 15V V_IN e 15V
b0 64
b1 6
b4 2
b0 51 b0 88
b1 3 b2 2
b3 4 b8
b0 36
mA
b0 90
mA
b2 4
mA
b0 10
0 10
b10^b5 b0 10
10^b5 0 10
b1 0 mA
1 0 mA
Schematic Diagram
CD4023BC CD4023BM
Device Shown
All Inputs Protected
by Standard CMOS Input
Protection Circuit
TL F 5956 – 3
2