OPA2835 Datasheet, PDF (27/53 Pages) National Semiconductor (TI) – Ultra Low-Power, Rail-to-Rail Out, Negative Rail In, VFB Op Amp

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OPA835
OPA2835
SLOS713E – JANUARY 2011 – REVISED JULY 2013
Integrated solutions are available, but the OPA835 provides a much lower power high frequency solution. For
best CMRR performance, resistors must be matched. A rule of thumb is CMRR ≈ the resistor tolerance; so 0.1%
tolerance will provide about 60 dB CMRR.
Gain Setting with OPA835 RUN Integrated Resistors
The OPA835 RUN package option includes integrated gain setting resistors for smallest possible footprint on a
printed circuit board (≈ 2mm x 2mm). By adding circuit traces on the PCB, gains of +1, -1, -1.33, +2, +2.33, -3,
+4, -4, +5, -5.33, +6.33, -7, +8 and inverting attenuations of -0.1429, -0.1875, -0.25, -0.33, -0.75 can be
achieved.
Figure 60 shows a simplified view of how the OPA835IRUN integrated gain setting network is implemented.
Table 1 shows the required pin connections for various non-inverting and inverting gains (reference Figure 53
and Figure 54). Table 2 shows the required pin connections for various attenuations using the inverting amplifier
architecture (reference Figure 54). Due to ESD protection devices being used on all pins, the absolute maximum
and minimum input voltage range, V_S– - 0.7V to V_S+ + 0.7V, applies to the gain setting resistors, and so
attenuation of large input voltages will require external resistors to implement.
The gain setting resistors are laser trimmed to 1% tolerance with nominal values of 2.4 kΩ, 1.8 kΩ, and 600 Ω.
They have excellent temperature coefficient and gain tracking is superior to using external gain setting resistors.
The 800 Ω and 1.25 pF capacitor in parallel with the 2.4 kΩ gain setting resistor provide compensation for best
stability and pulse response.
FB1
FB2
9
8
2.4 k
FB3
7
1.8 k
FB4
6
600
800 1.25 pF
Figure 60. OPA835IRUN Gain Setting Network
Non-inverting Gain
(Figure 53)
1 V/V (0 dB)
2 V/V (6.02 dB)
2.33 V/V (7.36 dB)
4 V/V (12.04 dB)
5 V/V (13.98 dB)
6.33 V/V (16.03 dB)
8 V/V (18.06 dB)
Inverting Gain
(Figure 54)
-
-1 V/V (0 dB)
-1.33 V/V (2.5 dB)
-3 V/V (9.54 dB)
-4 V/V (12.04 dB)
-5.33 V/V (14.54 dB)
-7 V/V (16.90 dB)
Table 1. Gains Setting
Short Pins
1 to 9
1 to 9
1 to 9
1 to 8
1 to 9
1 to 9
1 to 9
Short Pins
2 to 8
2 to 8
2 to 7
2 to 7 or 8
2 to 6 or 8
2 to 7
Short Pins
6 to GND
7 to GND
6 to GND
7 to 8
6 to 8
6 to GND
Inverting Gain
(Figure 54)
-0.75 V/V (-2.5 dB)
-0.333 V/V (-9.54 dB)
-0.25 V/V (-12.04 dB)
-0.1875 V/V (-14.54 dB)
-0.1429 V/V (-16.90 dB)
Table 2. Attenuator Settings
Short Pins
1 to 7
1 to 6
1 to 6
1 to 7
1 to 6
Short Pins
2 to 8
2 to 7
2 to 7 or 8
2 to 6 or 8
2 to 7
Short Pins
9 to GND
8 to GND
7 to 8
6 to 8
9 to GND
Short Pins
-
-
-
-
6 to GND
7 to GND
-
Short Pins
-
-
9 to GND
9 to GND
-
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