LMH6629_1011 Datasheet, PDF (25/28 Pages) National Semiconductor (TI) – Ultra-Low Noise, High-Speed Operational Amplifier with Shutdown

LAYOUT CONSIDERATIONS
National Semiconductor offers evaluation board(s) to aid in
device testing and characterization and as a guide for proper
layout. As is the case with all high-speed amplifiers, accepted-
practice RF design technique on the PCB layout is mandato-
ry. Generally, a good high-frequency layout exhibits a
separation of power supply and ground traces from the in-
verting input and output pins. Parasitic capacitances between
these nodes and ground may cause frequency response
peaking and possible circuit oscillations (see Application Note
OA-15 for more information). Use high-quality chip capacitors
with values in the range of 1000 pF to 0.1F for power supply
bypassing. One terminal of each chip capacitor is connected
to the ground plane and the other terminal is connected to a
point that is as close as possible to each supply pin as allowed
by the manufacturer’s design rules. In addition, connect a
tantalum capacitor with a value between 4.7 μF and 10 μF in
parallel with the chip capacitor.
Harmonic Distortion, especially HD2, is strongly influenced by
the layout and in particular can be affected by decoupling ca-
pacitors placed between the V⁺ and V^- terminals as close to
the device leads as possible.
Signal lines connecting the feedback and gain resistors
should be as short as possible to minimize inductance and
microstrip line effect. Place input and output termination re-
sistors as close as possible to the input/output pins. Traces
greater than 1 inch in length should be impedance matched
to the corresponding load termination.
Symmetry between the positive and negative paths in the
layout of differential circuitry should be maintained to mini-
mize the imbalance of amplitude and phase of the differential
signal.
Component value selection is another important parameter in
working with high-speed / high-performance amplifiers.
Choosing external resistors that are large in value compared
to the value of other critical components will affect the closed
loop behavior of the stage because of the interaction of these
resistors with parasitic capacitances. These parasitic capac-
itors could either be inherent to the device or be a by-product
of the board layout and component placement. Moreover, a
large resistor will also add more thermal noise to the signal
path. Either way, keeping the resistor values low will diminish
this interaction. On the other hand, choosing very low value
resistors could load down nodes and will contribute to higher
overall power dissipation and high distortion.
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