LMH0340_09 Datasheet, PDF (21/26 Pages) National Semiconductor (TI) – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver with LVDS Interface

ADD
'h
27
28
29
2A
2B-2D
2E
2F
Name
Bits
Field
R/W Default Description
Event Disable
The SER keeps counts of various types of events. These include FIFO over/underflows, and loss
of the input signals or clocks. This register allows the user to mask these errors from being
counted.
7:5
Reserved
4
PLL_CLK_disable r/w
0'b
1: Clock Error disabled
0: Clock Errors counted
3
fifo_error_disable r/w
0'b
1: FIFO Errors ignored
0: FIFO Errors counted
2
TXCLK_detect_disa r/w
0'b
1: TXCLK Detect Errors ignored
ble
0: TXCLK Detect Errors counted
1
CLK_LOS_disable r/w
0'b
1: CLK_LOS Errors ignored
0: CLK_LOS Errors counted
0
Data_LOS_disable r/w
0'b
1: Data_LOS Errors ignored
0: Data_LOS Errors counted
LVDS LOS
These bits are used to force the LOS indicator regardless of the input signal level on the LVDS
Override Operation pins.
7:2
Reserved
1
LVDS Preset LOS r/w
0'b
LVDS Preset LOS
1: Forces LOS to be Low
0: normal mode
0
LVDS Reset LOS r/w
0'b
LVDS Reset LOS
(has priority over Preset)
1: Forces LOS to be High
0: normal mode
LOS Status
Reading the LOS status register will provide a byte which has six bits which represent the
presence or absence of a signal at each of the LVDS inputs to the SER.
7:6
Reserved
5
LOS_CLK
r
0'b
1: No clock present on TXCLK
0: Clock present
4:0
LOS_Data
r
0'b
1:No data present
0: Data Present(one bit per TX channel)
Event Status
The event status register has two user readable bits which indicate if the device is locked, and if
there is a signal present on the TXCLK input.
7:4
Reserved
3
TXCLK_detect
r
0'b
1: TXCLK detected
0: TXCLK not detected
2
PLL_lock
r
0'b
1: PLL locked
0: PLL not locked
1:0
Reserved
Reserved
Reverse Bit Order This bit can be used to reverse the serialization order, however it will only work properly when
the device is NOT in DVB_ASI mode
7
Reserved
6
Reverse Bit Order r/w
0'b
1: reverses serialization order
0: normal order
5:0
Reserved
Reserved
21
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