LMH0340_09 Datasheet, PDF (10/26 Pages) National Semiconductor (TI) – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver with LVDS Interface

CML Output Interfacing
The LMH0050 does not include the internal SMPTE cable
driver, as its outputs are CML, include internal 50 Ω pull up
resistors, and are intended to drive 100 Ω transmission lines.
The LMH0050 outputs may either be connected to a differ-
ential transmission medium such as twisted pair cable, or
used to drive an external cable driver.
Power Down Mode
If the device is not to be used, some power can be saved by
writing a ‘0x40h’ to register 0x26'h, and a 0x10'h to register
0x01'h. The write to register 0x26'h will disable the input
buffers of the device, and the write to register 0x01'h will pow-
er down the output buffer. In this mode, the device power
dissipation can be expected to be reduced by approximately
30%. There are portions of the circuit which will automatically
power down if there is no clock present on the TXCLK input,
so this method can be used to further reduce the power.
SMBus INTERFACE
The configuration bus conforms to the System Management
Bus (SMBus) 2.0 specification. SMBus 2.0 includes multiple
options. The optional ARP (Address Resolution Protocol) fea-
ture is not supported. The I/O rail is 3.3V only and is not 5V
tolerant. The use of the SMB_CS signal is recommended for
applications with multi-drop applications (multiple devices to
a host).
The SMBus is a two wire interface designed for the commu-
nication between various system component chips, additional
signals maybe required for chip select function depending
upon application. By accessing the control functions of the
circuit via the SMBus, signal count is kept to a minimum while
allowing a maximum amount of versatility. The SMBus has
three pins to control it: an SMBus CS pin which enables the
SMBus interface for the device, a Clock and a Data line. In
applications where there might be several SER devices, the
SDA and SCK pins can be bussed together and the individual
devices to be communicated with may be selected via their
respective SMB_CS pin. The SCK and SDA are both open
drain and are pulled high by external pullup resistors. The
SER has several internal configuration registers which may
be accessed via the SMBus. These registers are listed in SER
Register Detail Table.
TRANSFER OF DATA TO THE DEVICE VIA THE SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SCK is high.
START / STOP / IDLE CONDITIONS
There are three unique states for the SMBus:
START A HIGH-to-LOW transition on SDA while SCK is
High indicates a message START condition
STOP A LOW-to-HIGH transition on SDA while SCK is
High indicates a message STOP condition.
IDLE
If SCK and SDA are both High for a time exceeding
t_BUF from the last detected STOP condition or if they
are high for a total exceeding the maximum
specification for t_HIGH then the bus will transfer to the
IDLE state.
SMBus TRANSACTIONS
A transaction begins with the host placing the SER SMBus
into the START condition. Then a byte (8 bits) is transferred,
MSB first, followed by a ninth ACK bit. ACK bits are ‘0’ to sig-
nify an ACK, or ‘1’ to signify NACK. After this the host holds
the SCK line Low, and waits for the receiver to raise the SDA
line as an ACKnowledge that the byte has been received.
REGISTER WRITE
To write a data value to a register in the SER, the host writes
three bytes to the SER. The first byte is the device address—
the device address is a 7 bit value, and if writing to the SER
the last bit (LSB) is set to ‘0’ to signify that the operation is a
write. The second byte written is the register address, and the
third byte written is the data to be written into the addressed
register. If additional data writes are performed, the register
address is automatically incremented. At the end of the write
cycle the host places the bus in the STOP state.
REGISTER READ
To read the data value from a register, first the host writes the
device address with the LSB set to a ‘0’ denoting a write, and
then the register address is written to the device. The host
then reasserts the START condition, and writes the device
address once again, but this time with the LSB set to a ‘1’
denoting a read, and following this the SER will drive the SDA
line with the data from the addressed register. The host indi-
cates that it has finished reading the data by asserting a ‘0’
for the ACK bit. After reading the last byte, the host will assert
a ‘1’ for NACK to indicate to the SER that it does not require
any more data.
Note that the SMBus pins are not 5V compliant and they
must be driven by a 3.3V source.
SMBus CONFIGURATIONS
Many different configurations of the SMBus are possible and
depend upon the specific requirements of the applications.
Several possible applications are described.
CONFIGURATION 1
The SER SMB_CS may be tied High (always enabled) since
it is the only device on the SMBus. See Figure 8.
CONFIGURATION 2
Since the multiple SER devices have the same address, the
use of the individual SMB_CS signals is required. To com-
municate with a specific device, its SMB_CS is driven High to
select the device. After the transaction is complete, its
SMB_CS is driven Low to disable its SMB interface. Other
devices on the bus may now be selected with their respective
chip select signals and communicated with. See Figure 9.
CONFIGURATION 3
The addressing field is limited to 7-bits by the SMBus protocol.
Thus it is possible that multiple devices may share the same
7-bit address. An optional feature in the SMBus 2.0 specifi-
cation supports an Address Resolution Protocol (ARP). This
optional feature is not supported by the
LMH0340/0040/0070/0050 devices. Solutions for this in-
clude: the use of the independent SMB_CS signals, indepen-
dent SMBus segments, or other means. See Figure 10.
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