LMH0340_09 Datasheet, PDF (17/26 Pages) National Semiconductor (TI) – 3 Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver with LVDS Interface

SERIAL JITTER OPTIMIZATION
The SER is capable of very low jitter operation, however it is
dependent on the TXCLK provided by the host in order to op-
erate, and depending on the quality of the TXCLK provided,
the SER output jitter may not be as low as it could be.
The SER includes circuitry to filter out any TXCLK jitter at fre-
quencies above 1MHz (see Figure 15), however, for frequen-
cies below 100 kHz, any jitter that is in the TXCLK is passed
directly through to the serialized output.
In most cases, passing the TXCLK through the FPGA will add
high frequency noise to the signal, which will be filtered out
by the SER, resulting in a clean output, however for better
jitter performance, it is best to minimize the noise that is on
the TXCLK that is provided to the SER. This can be done by
careful routing of the CLK signals, both within the FPGA and
on the board.
Very clean clocks can be derived from video reference signals
through the use of the LMH1981 Sync Separator and the
LMH1982 Clock Generator products from National Semicon-
ductor. These products allow low jitter video frequency clocks
to be generated either independently, or phase locked to a
video reference signal.
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FIGURE 15. SER Jitter Transfer Function
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