LMH6574 Datasheet, PDF (2/15 Pages) National Semiconductor (TI) – 4:1 High Speed Video Multiplexer

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance
Human Body Model
Machine Model
Supply Voltage (V⁺ − V^−)
I_OUT (Note 3)
Signal & Logic Input Pin Voltage
Signal & Logic Input Pin Current
Maximum Junction Temperature
(Note 4)
2000V
200V
13.2V
130 mA
±(V_S+0.6V)
±20 mA
+150˚C
Storage Temperature Range
Soldering Information
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
−65˚C to +150˚C
235 ˚C
260 ˚C
Operating Ratings (Note 1)
Operating Temperature
Supply Voltage Range
Thermal Resistance
Package
14-Pin SOIC
−40 ˚C to 85 ˚C
6V to 12V
(θ_JA)
130˚C/W
(θ_JC)
40˚C/W
±5V Electrical Characteristics
V_S = ±5V, R_L = 100Ω, A_V=2 V/V, T_J=25 ˚C, Unless otherwise specified. Bold numbers specify limits at temperature extremes.
Symbol
Parameter
Conditions (Note 2)
Min
Typ
Max
Units
Frequency Domain Performance
SSBW
LSBW
.1 dBBW
DG
DP
XTLK
−3 dB Bandwidth
–3 dB Bandwidth
0. 1 dB Bandwidth
Differential Gain
Differential Phase
Channel to Channel Crosstalk
V_OUT = 0.5V_PP
V_OUT = 2V_PP
V_OUT = 0.25V_PP
R_L = 150Ω, f=4.43 MHz
R_L = 150Ω, f=4.43MHz
All Hostile, 5MHz
500
MHz
400
MHz
150
MHz
0.02
%
0.05
deg
−85
dB
Time Domain Response
TRS
Channel to Channel Switching Time Logic transition to 90% output
8
ns
Enable and Disable Times
Logic transition to 90% or 10%
output.
10
ns
TRL
Rise and Fall Time
4V Step
2.4
ns
TSS
Settling Time to 0.05%
2V Step
17
ns
OS
Overshoot
2V Step
5
%
SR
Slew Rate
4V Step
2200
V/µs
Distortion
HD2
2^nd Harmonic Distortion
2V_PP , 5 MHz
−68
dBc
HD3
3^rd Harmonic Distortion
2V_PP , 5 MHz
−84
dBc
IMD
3^rd Order Intermodulation Products 10MHz, Two tones 2Vpp at output
−80
dBc
Equivalent Input Noise
VN
Voltage
ICN
Current
>1MHz, Input Referred
>1MHz, Input Referred
5
nV
5
pA/
Static, DC Performance
CHGM Channel to Channel Gain
Difference
VIO
Input Offset Voltage (Note 5)
DC, Difference in gain between
channels
V_IN = 0V
±0.005 ±0.032
%
±0.035
1
±20
mV
±25
DVIO
IBN
Offset Voltage Drift
Input Bias Current (Notes 7, 5)
V_IN = 0V
30
µV/˚C
−3
±5
µA
±5.6
DIBN
Bias Current Drift
Inverting Input Bias Current
PSRR
Power Supply Rejection Ratio
(Note 5)
Pin 12, Feedback point,
V_IN = 0V
DC, Input referred
11
nA/˚C
−7
±10
±13
47
54
dB
45
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