LMH6574 Datasheet, PDF (13/15 Pages) National Semiconductor (TI) – 4:1 High Speed Video Multiplexer

Other Applications (Continued)
output under capacitive loading. Capacitive loads of
5 to 120 pF are the most critical, causing ringing, frequency
response peaking and possible oscillation. The chart “Sug-
gested R_OUT vs. Cap Load” gives a recommended value for
selecting a series output resistor for mitigating capacitive
loads. The values suggested in the charts are selected for
0.5 dB or less of peaking in the frequency response. This
gives a good compromise between settling time and band-
width. For applications where maximum frequency response
is needed and some peaking is tolerable, the value of R_OUT
can be reduced slightly from the recommended values.
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FIGURE 6. Decoupling Capacitive Loads
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FIGURE 7. Suggested R_OUT vs. Capacitive Load
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FIGURE 8. Frequency Response vs. Capacitive Load
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation
board as a guide. The LMH730276 is the evaluation board
supplied with samples of the LMH6574. To reduce parasitic
capacitances, ground and power planes should be removed
near the input and output pins. For long signal paths con-
trolled impedance lines should be used, along with imped-
ance matching elements at both ends. Bypass capacitors
should be placed as close to the device as possible. Bypass
capacitors from each rail to ground are applied in pairs. The
larger electrolytic bypass capacitors can be located farther
from the device, the smaller ceramic capacitors should be
placed as close to the device as possible. In Figure 1, the
capacitor between V⁺ and V^− is optional, but is recom-
mended for best second harmonic distortion. Another way to
enhance performance is to use pairs of 0.01µF and 0.1µF
ceramic capacitors for each supply bypass.
POWER DISSIPATION
The LMH6574 is optimized for maximum speed and perfor-
mance in the small form factor of the standard SOIC pack-
age. To ensure maximum output drive and highest perfor-
mance, thermal shutdown is not provided. Therefore, it is of
utmost importance to make sure that the T_JMAX is never
exceeded due to the overall power dissipation.
Follow these steps to determine the Maximum power dissi-
pation for the LMH6574:
1. Calculate the quiescent (no-load) power: P_AMP = I_CC*
(V_S), where V_S = V⁺ - V^−.
2. Calculate the RMS power dissipated in the output stage:
P_D (rms) = rms ((V_S - V_OUT) * I_OUT), where V_OUT and
I_OUT are the voltage across and the current through the
external load and V_S is the total supply voltage.
3. Calculate the total RMS power: P_T = P_AMP + P_D.
The maximum power that the LMH6574 package can dissi-
pate at a given temperature can be derived with the following
equation:
P_MAX = (150˚ – T_AMB)/ θ_JA, where T_AMB = Ambient tempera-
ture (˚C) and θ_JA = Thermal resistance, from junction to
ambient, for a given package (˚C/W). For the SOIC package
θ_JA is 130 ˚C/W.
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