LMC2626 Datasheet, PDF (2/6 Pages) National Semiconductor (TI) – CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems

Absolute Maximum Ratings (Note 1)
ESD Tolerance 2 kV HBM 200V MM (Note 4)
Sync Input Voltage
P5V
Supply Voltage (V_IN P5V)
Continuous Total Power Dissipation (Note 1)
6 3V
Lead Temperature (less than 10 sec)
260 C
Storage Temperature Range
b65 C to a150 C
Junction Temperature
150 C
Operating Ratings (Note 1)
V_IN Supply Voltage
P5V Supply Voltage (Note 5)
4 5V ^s V_IN ^s 5 5V
4 8V ^s P5V ^s 5 2V
Junction Temperature Range
b25 C to a125 C
Ambient Temperature Range
b40 C to a85 C
DC Electrical Characteristics
Unless otherwise specified all limits guaranteed for b20 C ^s T_A ^s a85 C P5V e 5V and 4 5V ^s V_IN ^s 5 5V V_REF e 1 227V
SYNC(OPEN) SD(OPEN) ^k P5V e V_IN e 5V
VSH LDO Voltage Regulator (Notes 7 10 11)
Symbol
V_O(VREF)
I_VREF
V_SH
DV_SH
V_DO
I_S(VIN)
T_SD
I_OUT
Parameter
V_REF Voltage Level
in Shutdown
DC Current from
V_REF Pin
Output Voltage on
V_SH Pin (see Note 2)
Variation of V_SH over
Temperature
LDOR Voltage Dropout
(V_IN – V_SH)
V_IN Supply Current
Load Regulation of LDO
Voltage Regulation
Line Regulation of LDOR
Thermal Shutdown
Threshold
Output Load Current
Conditions
SD e 0V
I_VREF e b1 mA
V_IN e 5V
4 5V ^s V_IN ^s 5 5V
20 mA ^s IL ^s 150 mA
1 218 ^s V_REF ^s 1 242
4 5V ^s V_IN ^s 5 5V
20 mA ^s IL ^s 150 mA
IL e 150 mA
4 5V ^s V_IN ^s 5 5V
20 mA ^s IL ^s 150 mA
4 5V ^s V_IN ^s 5 5V
20 mA ^s IL ^s 150 mA
(see Note 8)
(see Note 2)
Min
4 00
b40 0
4 10
230
Typ
(Note 9)
4 76
b13 3
4 20
4
0 17
394
0 002
0 24
160
Max
b5
4 30
126
0 30
500
0 015
0 95
300
Units
V
mA
V
mV
V
mA
% mA
%V
C
mA
Shutdown Control (Note 8)
Symbol
I_IL(SD)
I_IH(SD)
I_s(SD)
C_in(SYNC)
Parameter
Low Level Input Current
for SD Pin
High Level Input Current
for SD Pin
V_IN Supply Current
in Shutdown Mode
Input Capacitance
at SYNC Pin (Note 6)
Conditions
V_IN e 5V
SD e 0V
SD e 5V
SYNC e 5V
T_A e 27 C
Min
b300
180
Typ
(Note 9)
b217
310
285
20
Max
b150
1000
400
Units
mA
nA
mA
pF
2