LMC2626 Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – CMOS LDOR/Buffer Chip for Row Inversion Flat Panel Display Systems

PRELIMINARY
November 1995
LMC2626
CMOS LDOR Buffer Chip for Row
Inversion Flat Panel Display Systems
General Description
The LMC2626 integrated circuit is specifically developed for
a row inversion TFT FPD system architecture It is designed
only to be used in conjunction with National’s LM2625
switching regulator chip
Built on National’s advanced CMOS CS80 process this chip
generates a high-power precision square-wave from a digi-
tal sync signal The chip also contains thermal shutdown
circuitry system shutdown circuitry and a low drop-out volt-
age regulator to generate a 4 2 volt supply from an external-
ly applied reference voltage of 1 227V
Features
Y _{Used in conjunction with LM2625 chip}
Y _{High output current buffer}
Y _{Low buffer on resistance}
Y _{System shutdown control}
Y _{LDO voltage regulator}
Y _{LDOR dropout 0 3V maximum at 150 mA}
Y _{Thermal shutdown short circuit protection}
Y _{External reference required for LDOR}
Y _{VREF pin converts to a digital pin to shutdown LM2625}
Connection Diagram
Pin Description
8-Pin SO
Pin Pin Name
Description
1
V_REF
1 218V to 1 242V Ext Reference
from LM2625 (see Note 8)
2 SD
System Shutdown input pin for
LMC2626 and LMC2625
3 SYNC
Digital input square wave from FPD
controller
4 GND
Ground
5 P5V
Precision Regulated a5V Supply
6
V_OUT
7
V_IN
Power Buffer Output
FPD System Supply (a4 5V to
a5 5V)
8
V_SH
Low Drop-Out Voltage Regulator
Output
Top View
TL H 12541 – 1
Ordering Information
Package
8-Pin SO
Temperature Range
b40 C to a85 C
LMC2626IM
NSC
Drawing
M08A
Transport
Media
Rail
Tape and
Reel
C1996 National Semiconductor Corporation TL H 12541
RRD-B30M26 Printed in U S A