DS91C176_08 Datasheet, PDF (2/14 Pages) National Semiconductor (TI) – 100 MHz Single Channel M-LVDS Transceivers

Connection and Logic Diagram
Top View
20024601
Order Number DS91D176TMA, DS91C176TMA
See NS Package Number M08A
Ordering Information
Order Number
DS91D176TMA
DS91C176TMA
Receiver Input
type 1
type 2
Function
Data (0V threshold receiver)
Control (100 mV offset fail-safe receiver)
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different
types of receiver input stages. A type 1 receiver has a con-
ventional threshold that is centered at the midpoint of the input
amplitude, V_ID/2. A type 2 receiver has a built in offset that is
100mV greater than V_ID/2. The type 2 receiver offset acts as
a failsafe circuit where open or short circuits at the input will
always result in the output stage being driven to a low logic
state.
Package Type
SOIC/M08A
SOIC/M08A
20024640
FIGURE 1. M-LVDS Receiver Input Thresholds
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